diff --git a/include/uapi/display/drm/sde_drm.h b/include/uapi/display/drm/sde_drm.h
index 5eee6bd87e..1c5b87ff2d 100644
--- a/include/uapi/display/drm/sde_drm.h
+++ b/include/uapi/display/drm/sde_drm.h
@@ -268,6 +268,7 @@ struct sde_drm_de_v1 {
 #define SDE_DRM_QSEED3LITE
 #define SDE_DRM_QSEED4
 #define SDE_DRM_INLINE_PREDOWNSCALE
+#define SDE_DRM_QSEED6
 
 /**
  * struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler
@@ -309,6 +310,8 @@ struct sde_drm_de_v1 {
  * @de_lpf_h:          Detail enhancer lpf blend high
  * @de_lpf_l:          Detail enhancer lpf blend low
  * @de_lpf_m:          Detail enhancer lpf blend medium
+ * @dir45_en:          45/-45 degree direction filtering enable
+ * @cor_en:            corner enhancer enable
  */
 struct sde_drm_scaler_v2 {
 	/*
@@ -379,6 +382,8 @@ struct sde_drm_scaler_v2 {
 	__u32 de_lpf_h;
 	__u32 de_lpf_l;
 	__u32 de_lpf_m;
+	__u32 dir45_en;
+	__u32 cor_en;
 };
 
 /* Number of dest scalers supported */
diff --git a/msm/sde/sde_hw_reg_dma_v1_color_proc.c b/msm/sde/sde_hw_reg_dma_v1_color_proc.c
index 4ff08da28b..64a3a252fd 100644
--- a/msm/sde/sde_hw_reg_dma_v1_color_proc.c
+++ b/msm/sde/sde_hw_reg_dma_v1_color_proc.c
@@ -3392,6 +3392,8 @@ void reg_dmav1_setup_vig_qseed3(struct sde_hw_pipe *ctx,
 
 	op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
 	op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
+	op_mode |= (scaler3_cfg->dir_en && scaler3_cfg->cor_en) ? BIT(5) : 0;
+	op_mode |= (scaler3_cfg->dir_en && scaler3_cfg->dir45_en) ? BIT(6) : 0;
 	op_mode |= (scaler3_cfg->dyn_exp_disabled) ? BIT(13) : 0;
 
 	preload =
diff --git a/msm/sde/sde_hw_util.c b/msm/sde/sde_hw_util.c
index d2b9615511..8da062f767 100644
--- a/msm/sde/sde_hw_util.c
+++ b/msm/sde/sde_hw_util.c
@@ -115,6 +115,8 @@ void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,
 
 	cfg->enable = scale_v2->enable;
 	cfg->dir_en = scale_v2->dir_en;
+	cfg->dir45_en = scale_v2->dir45_en;
+	cfg->cor_en = scale_v2->cor_en;
 
 	for (i = 0; i < SDE_MAX_PLANES; i++) {
 		cfg->init_phase_x[i] = scale_v2->init_phase_x[i];
@@ -376,6 +378,8 @@ void sde_hw_setup_scaler3(struct sde_hw_blk_reg_map *c,
 
 	op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
 	op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
+	op_mode |= (scaler3_cfg->dir_en && scaler3_cfg->cor_en) ? BIT(5) : 0;
+	op_mode |= (scaler3_cfg->dir_en && scaler3_cfg->dir45_en) ? BIT(6) : 0;
 	op_mode |= (scaler3_cfg->dyn_exp_disabled) ? BIT(13) : 0;
 
 	preload =
diff --git a/msm/sde/sde_hw_util.h b/msm/sde/sde_hw_util.h
index 730cd64703..a791e00da1 100644
--- a/msm/sde/sde_hw_util.h
+++ b/msm/sde/sde_hw_util.h
@@ -78,6 +78,8 @@ struct sde_hw_scaler3_de_cfg {
  * struct sde_hw_scaler3_cfg : QSEEDv3 configuration
  * @enable:        scaler enable
  * @dir_en:        direction detection block enable
+ * @dir45_en:      45/-45 degree direction filtering block enable
+ * @cor_en:        corner detection block enable
  * @ init_phase_x: horizontal initial phase
  * @ phase_step_x: horizontal phase step
  * @ init_phase_y: vertical initial phase
@@ -118,6 +120,8 @@ struct sde_hw_scaler3_de_cfg {
 struct sde_hw_scaler3_cfg {
 	u32 enable;
 	u32 dir_en;
+	u32 dir45_en;
+	u32 cor_en;
 	int32_t init_phase_x[SDE_MAX_PLANES];
 	int32_t phase_step_x[SDE_MAX_PLANES];
 	int32_t init_phase_y[SDE_MAX_PLANES];