From a7525bef97e434b5b99042ead8dc9ea28d6542a3 Mon Sep 17 00:00:00 2001 From: Jayaprakash Madisetty Date: Tue, 11 Jun 2024 12:20:09 +0530 Subject: [PATCH 1/3] disp: msm: sde: update register_dump_range check in sde_dbg Add changes to update the register_dump_range offset_start and offset_end validation introduced as part of 'commit cfc54d3f2223 ("disp: msm: sde: add check to avoid registering invalid ranges in dump")'. Change-Id: I5e4332687b37d7926afdce6903d8fea6ce2874b1 Signed-off-by: Jayaprakash Madisetty --- msm/sde_dbg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/msm/sde_dbg.c b/msm/sde_dbg.c index 8b44539270..31e7d9080f 100644 --- a/msm/sde_dbg.c +++ b/msm/sde_dbg.c @@ -2874,7 +2874,7 @@ void sde_dbg_reg_register_dump_range(const char *base_name, return; } - if (!offset_start || !offset_end || (offset_start > offset_end)) { + if ((!offset_start && !offset_end) || (offset_start > offset_end)) { pr_info("%pS: bad range, base_name %s, range_name %s, offset_start 0x%X, end 0x%X\n", __builtin_return_address(0), base_name, range_name, offset_start, offset_end); From 0d3c4d5ac14f00bc985d0461d180213a9e49f436 Mon Sep 17 00:00:00 2001 From: Akhil Jaiswal Date: Thu, 13 Jun 2024 16:38:21 +0530 Subject: [PATCH 2/3] disp: msm: sde: fix cwb crop ctrl enablement flow When partial fb is sent from userspace to dump only partial frame roi, cwb crop feature needs to be enabled. 'commit fded00588190 ("disp: msm: sde: add support for CWB + single LM partial update")' is overriding this crop ctrl enable bit. Due to this cwb xin is idle always and wb timeouts are seen. Add changes to move the cwb setup with false to happen early to fix overriding the crop ctrl enablement. Change-Id: If187319d59026f43db71e6655a74bfd62acf2dc3 Signed-off-by: Akhil Jaiswal --- msm/sde/sde_encoder_phys_wb.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/msm/sde/sde_encoder_phys_wb.c b/msm/sde/sde_encoder_phys_wb.c index 3a5e618fe1..88aaaf1458 100644 --- a/msm/sde/sde_encoder_phys_wb.c +++ b/msm/sde/sde_encoder_phys_wb.c @@ -1823,17 +1823,18 @@ static void sde_encoder_phys_wb_setup(struct sde_encoder_phys *phys_enc) sde_encoder_phys_setup_cdm(phys_enc, fb, wb_enc->wb_fmt, wb_roi); - sde_encoder_phys_wb_setup_fb(phys_enc, fb, wb_roi, out_width, out_height); - - _sde_encoder_phys_wb_setup_ctl(phys_enc, wb_enc->wb_fmt); - - _sde_encoder_phys_wb_setup_sys_cache(phys_enc, fb); /* clear existing intf cwb configuration before * updating for single LM PartialUpdate usecase. */ if (_sde_encoder_is_single_lm_partial_update(wb_enc)) _sde_encoder_phys_wb_setup_cwb(phys_enc, false); + sde_encoder_phys_wb_setup_fb(phys_enc, fb, wb_roi, out_width, out_height); + + _sde_encoder_phys_wb_setup_ctl(phys_enc, wb_enc->wb_fmt); + + _sde_encoder_phys_wb_setup_sys_cache(phys_enc, fb); + _sde_encoder_phys_wb_setup_cwb(phys_enc, true); _sde_encoder_phys_wb_setup_prog_line(phys_enc); From 68257149e7d6fc9b96aa967819a5356793bad35d Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Fri, 7 Jun 2024 16:13:39 +0530 Subject: [PATCH 3/3] disp: msm: sde: factor qsync min fps in vblank time out update kickoff timeout based on qsync minimum frame rate. Change-Id: Ie9c80111bf5103fde0399921777ca64f76574a5a Signed-off-by: Akash Gajjar --- msm/sde/sde_encoder.c | 8 ++++++++ msm/sde/sde_encoder_phys_cmd.c | 4 +++- msm/sde/sde_encoder_phys_vid.c | 2 ++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/msm/sde/sde_encoder.c b/msm/sde/sde_encoder.c index f312ddeb29..c790edb54a 100644 --- a/msm/sde/sde_encoder.c +++ b/msm/sde/sde_encoder.c @@ -5472,6 +5472,7 @@ u32 sde_encoder_helper_get_kickoff_timeout_ms(struct drm_encoder *drm_enc) struct drm_encoder *src_enc = drm_enc; struct sde_encoder_virt *sde_enc; struct sde_kms *sde_kms; + u32 qsync_mode = 0, qsync_min_fps = 0; u32 fps; if (!drm_enc) { @@ -5495,6 +5496,13 @@ u32 sde_encoder_helper_get_kickoff_timeout_ms(struct drm_encoder *drm_enc) sde_enc = to_sde_encoder_virt(src_enc); fps = sde_enc->mode_info.frame_rate; + if (sde_enc->cur_master) + qsync_mode = sde_connector_get_qsync_mode(sde_enc->cur_master->connector); + + qsync_min_fps = sde_enc->mode_info.qsync_min_fps; + if (qsync_mode && qsync_min_fps) + fps = min(fps, qsync_min_fps); + if (!fps || fps >= DEFAULT_TIMEOUT_FPS_THRESHOLD) return DEFAULT_KICKOFF_TIMEOUT_MS; else diff --git a/msm/sde/sde_encoder_phys_cmd.c b/msm/sde/sde_encoder_phys_cmd.c index 7a10231984..67b6077daa 100644 --- a/msm/sde/sde_encoder_phys_cmd.c +++ b/msm/sde/sde_encoder_phys_cmd.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ @@ -1849,6 +1849,8 @@ static int sde_encoder_phys_cmd_prepare_for_kickoff( sde_enc = to_sde_encoder_virt(phys_enc->parent); phys_enc->frame_trigger_mode = params->frame_trigger_mode; + phys_enc->kickoff_timeout_ms = + sde_encoder_helper_get_kickoff_timeout_ms(phys_enc->parent); SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(&phys_enc->pending_kickoff_cnt), atomic_read(&cmd_enc->autorefresh.kickoff_cnt), diff --git a/msm/sde/sde_encoder_phys_vid.c b/msm/sde/sde_encoder_phys_vid.c index c38d8c1791..a2f74fb7b2 100644 --- a/msm/sde/sde_encoder_phys_vid.c +++ b/msm/sde/sde_encoder_phys_vid.c @@ -1041,6 +1041,8 @@ static int sde_encoder_phys_vid_prepare_for_kickoff( } vid_enc = to_sde_encoder_phys_vid(phys_enc); + phys_enc->kickoff_timeout_ms = + sde_encoder_helper_get_kickoff_timeout_ms(phys_enc->parent); ctl = phys_enc->hw_ctl; if (!ctl->ops.wait_reset_status) return 0;