msm: camera: cpas: Update CPAS for v980

In CPAS v980, CAMNOC is split into RT and NRT. Camnoc RT and NRT each
has separate register base. Camnoc RT is used by TFE, IFE lite, RT CDM.
Camnoc NRT is used by OFE, IPE, ICP, JPEG, NRT CDM. There are also two
IRQ lines for CPAS: RT and NRT IRQs.

Add CPASTOP SBM IRQ for RT/NRT, static QOS NOC settings for RT/NRT,
Cesta, and others in the header file for v980. CPAS registers two IRQ
lines and handles the incoming (RT/NRT) IRQs based on the IRQ data for
each IRQ. CPAS SOC looks for IRQ identifier property in CPAS node DT
to classify the IRQ type.

Global Camnoc info variable and qchannel variable now contain separate
info for RT/NRT or combined info.

Add NRT reg base for camnoc NRT base. Add TFE UBWC Encode error.

CRs-Fixed: 3403163
Change-Id: I3044c6314fa65c4e486bfa1bff2e828ac5e285cd
Signed-off-by: Sokchetra Eung <[email protected]>

drivers/cam_cpas/cam_cpas_hw.c

@@ -17,7 +17,6 @@
 #include "cam_req_mgr_dev.h"
 #include "cam_smmu_api.h"
 #include "cam_compat.h"
-#include "cam_cpastop_hw.h"
 
 #define CAM_CPAS_LOG_BUF_LEN      512
 #define CAM_CPAS_APPLY_TYPE_START  1
@@ -638,40 +637,45 @@ static int cam_cpas_hw_dump_camnoc_buff_fill_info(
 	struct cam_hw_info *cpas_hw,
 	uint32_t client_handle)
 {
-	int rc = 0, i;
-	uint32_t val = 0;
+	int rc = 0, i, camnoc_idx;
+	uint32_t val = 0, client_idx = CAM_CPAS_GET_CLIENT_IDX(client_handle);
 	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
-	struct cam_camnoc_info *camnoc_info =
-		(struct cam_camnoc_info *) cpas_core->camnoc_info;
-	char log_buf[CAM_CPAS_LOG_BUF_LEN] = {0};
-	size_t len = 0;
+	struct cam_camnoc_info *camnoc_info;
+	char log_buf[CAM_CPAS_LOG_BUF_LEN];
+	size_t len;
 
-	if (!camnoc_info) {
-		CAM_ERR(CAM_CPAS, "Invalid camnoc info for hw_version: 0x%x",
-			cpas_hw->soc_info.hw_version);
-		return -EINVAL;
+	if (!CAM_CPAS_CLIENT_VALID(client_idx)) {
+		CAM_ERR(CAM_CPAS, "Invalid client idx: %u", client_idx);
+		return -EPERM;
 	}
 
-	for (i = 0; i < camnoc_info->specific_size; i++) {
-		if ((!camnoc_info->specific[i].enable) ||
-			(!camnoc_info->specific[i].maxwr_low.enable))
-			continue;
+	/* log buffer fill level of both RT/NRT NIU */
+	for (camnoc_idx = 0; camnoc_idx < cpas_core->num_valid_camnoc; camnoc_idx++) {
+		log_buf[0] = '\0';
+		len = 0;
+		camnoc_info = cpas_core->camnoc_info[camnoc_idx];
 
-		rc = cam_cpas_hw_reg_read(cpas_hw, client_handle,
-			CAM_CPAS_REG_CAMNOC,
-			camnoc_info->specific[i].maxwr_low.offset, true, &val);
-		if (rc)
-			break;
+		for (i = 0; i < camnoc_info->specific_size; i++) {
+			if ((!camnoc_info->specific[i].enable) ||
+				(!camnoc_info->specific[i].maxwr_low.enable))
+				continue;
 
-		len += scnprintf((log_buf + len), (CAM_CPAS_LOG_BUF_LEN - len),
-			" %s:[%d %d]", camnoc_info->specific[i].port_name,
-			(val & 0x7FF), (val & 0x7F0000) >> 16);
-	}
+			rc = cam_cpas_hw_reg_read(cpas_hw, client_handle,
+				camnoc_info->reg_base,
+				camnoc_info->specific[i].maxwr_low.offset, true, &val);
+			if (rc)
+				break;
 
-	CAM_INFO(CAM_CPAS, "CAMNOC Fill level [Queued Pending] %s", log_buf);
+			len += scnprintf((log_buf + len), (CAM_CPAS_LOG_BUF_LEN - len),
+				" %s:[%d %d]", camnoc_info->specific[i].port_name,
+				(val & 0x7FF), (val & 0x7F0000) >> 16);
+		}
 
-	return rc;
+		CAM_INFO(CAM_CPAS, "%s Fill level [Queued Pending] %s",
+			camnoc_info->camnoc_name, log_buf);
+	}
 
+	return rc;
 }
 
 static void cam_cpas_print_smart_qos_priority(
@@ -681,13 +685,18 @@ static void cam_cpas_print_smart_qos_priority(
 	struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
 	struct cam_cpas_private_soc *soc_private =
 		(struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
+	struct cam_camnoc_info *camnoc_info = NULL;
 	struct cam_cpas_tree_node *niu_node;
 	uint8_t i;
-	int32_t reg_indx = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC];
+	int32_t reg_indx;
 	char log_buf[CAM_CPAS_LOG_BUF_LEN] = {0};
 	size_t len = 0;
 	uint32_t val_low = 0, val_high = 0;
 
+	/* Smart QOS only apply to CPAS RT nius */
+	camnoc_info = cpas_core->camnoc_info[cpas_core->camnoc_rt_idx];
+	reg_indx = cpas_core->regbase_index[camnoc_info->reg_base];
+
 	for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
 		niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i];
 
@@ -702,7 +711,7 @@ static void cam_cpas_print_smart_qos_priority(
 			val_high, val_low);
 	}
 
-	CAM_INFO(CAM_CPAS, "SmartQoS [Node Pri_lut] %s", log_buf);
+	CAM_INFO(CAM_CPAS, "%s SmartQoS [Node Pri_lut] %s", camnoc_info->camnoc_name, log_buf);
 }
 
 static bool cam_cpas_is_new_rt_bw_lower(
@@ -952,14 +961,19 @@ static int cam_cpas_apply_smart_qos(
 	struct cam_cpas_private_soc *soc_private =
 		(struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
 	struct cam_cpas_tree_node *niu_node;
+	struct cam_camnoc_info *camnoc_info;
 	uint8_t i;
-	int32_t reg_indx = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC];
+	int32_t reg_indx;
 
 	if (cpas_core->smart_qos_dump) {
 		CAM_INFO(CAM_PERF, "Printing SmartQos values before update");
 		cam_cpas_print_smart_qos_priority(cpas_hw);
 	}
 
+	/* Smart QOS only apply to CPAS RT nius */
+	camnoc_info = cpas_core->camnoc_info[cpas_core->camnoc_rt_idx];
+	reg_indx = cpas_core->regbase_index[camnoc_info->reg_base];
+
 	for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
 		niu_node = soc_private->smart_qos_info->rt_wr_niu_node[i];
 
@@ -2778,6 +2792,12 @@ static int cam_cpas_hw_register_client(struct cam_hw_info *cpas_hw,
 
 	rc = cam_common_util_get_string_index(soc_private->client_name,
 		soc_private->num_clients, client_name, &client_indx);
+	if (rc) {
+		CAM_ERR(CAM_CPAS, "Client %s is not found in CPAS client list rc=%d",
+			client_name, rc);
+		mutex_unlock(&cpas_hw->hw_mutex);
+		return -ENODEV;
+	}
 
 	mutex_lock(&cpas_core->client_mutex[client_indx]);
 
@@ -2901,10 +2921,10 @@ static int cam_cpas_log_vote(struct cam_hw_info *cpas_hw, bool ddr_only)
 	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
 	struct cam_cpas_private_soc *soc_private =
 		(struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
-	uint32_t i;
+	uint32_t i, vcd_idx;
 	struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
-	struct cam_camnoc_info *camnoc_info =
-		(struct cam_camnoc_info *) cpas_core->camnoc_info;
+	struct cam_cpas_cesta_info *cesta_info =
+		(struct cam_cpas_cesta_info *)cpas_core->cesta_info;
 
 	if ((cpas_core->streamon_clients > 0) && soc_private->enable_smart_qos && !ddr_only)
 		cam_cpas_print_smart_qos_priority(cpas_hw);
@@ -2960,32 +2980,29 @@ static int cam_cpas_log_vote(struct cam_hw_info *cpas_hw, bool ddr_only)
 		void __iomem *cesta_base =
 			soc_info->reg_map[reg_base_index].mem_base;
 		uint32_t vcd_base_inc =
-			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.vcd_base_inc;
-		uint32_t num_vcds =
-			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.num_vcds;
+			cesta_info->cesta_reg_info->vcd_currol.vcd_base_inc;
+		uint32_t num_vcds = cesta_info->num_vcds;
 		uint32_t vcd_curr_lvl_base =
-			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.reg_offset;
+			cesta_info->cesta_reg_info->vcd_currol.reg_offset;
 		uint32_t cesta_vcd_curr_perfol_offset, cesta_vcd_curr_perfol_val;
 
 		if (!atomic_inc_not_zero(&cpas_core->soc_access_count))
 			goto skip_vcd_dump;
 
-		for (i = 0; i <= num_vcds; i++) {
-			if (i == camnoc_info->cesta_info->vcd_info[i].index) {
-				cesta_vcd_curr_perfol_offset = vcd_curr_lvl_base +
-					(vcd_base_inc * i);
-				cesta_vcd_curr_perfol_val =
-					cam_io_r_mb(cesta_base + cesta_vcd_curr_perfol_offset);
-				CAM_INFO(CAM_CPAS,
-					"i=%d, VCD[index=%d, type=%d, name=%s] [offset=0x%x, value=0x%x]",
-					i, camnoc_info->cesta_info->vcd_info[i].index,
-					camnoc_info->cesta_info->vcd_info[i].type,
-					camnoc_info->cesta_info->vcd_info[i].clk,
-					cesta_vcd_curr_perfol_offset,
-					cesta_vcd_curr_perfol_val);
-			} else {
-				CAM_WARN(CAM_CPAS, "cesta vcd index out of range");
-			}
+		for (i = 0; i < num_vcds; i++) {
+			vcd_idx = cesta_info->vcd_info[i].index;
+			cesta_vcd_curr_perfol_offset = vcd_curr_lvl_base +
+				(vcd_base_inc * vcd_idx);
+			cesta_vcd_curr_perfol_val =
+				cam_io_r_mb(cesta_base + cesta_vcd_curr_perfol_offset);
+
+			CAM_INFO(CAM_CPAS,
+				"i=%d, VCD[index=%d, type=%d, name=%s] [offset=0x%x, value=0x%x]",
+				i, cesta_info->vcd_info[i].index,
+				cesta_info->vcd_info[i].type,
+				cesta_info->vcd_info[i].clk,
+				cesta_vcd_curr_perfol_offset,
+				cesta_vcd_curr_perfol_val);
 		}
 
 		atomic_dec(&cpas_core->soc_access_count);
@@ -3070,22 +3087,14 @@ static void cam_cpas_update_monitor_array(struct cam_hw_info *cpas_hw,
 	const char *identifier_string, int32_t identifier_value)
 {
 	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
-	struct cam_camnoc_info *camnoc_info =
-		(struct cam_camnoc_info *) cpas_core->camnoc_info;
+	struct cam_camnoc_info *camnoc_info = NULL;
+	struct cam_cpas_cesta_info *cesta_info = cpas_core->cesta_info;
 	struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
 	struct cam_cpas_private_soc *soc_private =
 		(struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
 	struct cam_cpas_monitor *entry;
-	int iterator;
-	int i, j = 0;
-	int reg_camnoc = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC];
-	uint32_t val = 0;
-
-	if (!camnoc_info) {
-		CAM_ERR(CAM_CPAS, "Invalid camnoc info for hw_version: 0x%x",
-			cpas_hw->soc_info.hw_version);
-		return;
-	}
+	int iterator, i, j = 0, vcd_idx, camnoc_reg_idx;
+	uint32_t val = 0, camnoc_idx;
 
 	CAM_CPAS_INC_MONITOR_HEAD(&cpas_core->monitor_head, &iterator);
 
@@ -3158,65 +3167,73 @@ static void cam_cpas_update_monitor_array(struct cam_hw_info *cpas_hw,
 			cpas_core->regbase_index[CAM_CPAS_REG_CESTA];
 		void __iomem *cesta_base =
 			soc_info->reg_map[reg_base_index].mem_base;
-		uint32_t vcd_base_inc =
-			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.vcd_base_inc;
-		uint32_t num_vcds =
-			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.num_vcds;
-		uint32_t vcd_curr_lvl_base =
-			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.reg_offset;
+		uint32_t vcd_base_inc = cesta_info->cesta_reg_info->vcd_currol.vcd_base_inc;
+		uint32_t num_vcds = cesta_info->num_vcds;
+		uint32_t vcd_curr_lvl_base = cesta_info->cesta_reg_info->vcd_currol.reg_offset;
 		uint32_t cesta_vcd_curr_perfol_offset, cesta_vcd_curr_perfol_val;
 
 		if (atomic_inc_not_zero(&cpas_core->soc_access_count)) {
-			for (i = 0; i <= num_vcds; i++) {
-				if (i == camnoc_info->cesta_info->vcd_info[i].index) {
-					cesta_vcd_curr_perfol_offset = vcd_curr_lvl_base +
-						(vcd_base_inc * i);
-					cesta_vcd_curr_perfol_val =
-						cam_io_r_mb(cesta_base +
-						cesta_vcd_curr_perfol_offset);
-					entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[i].index =
-						camnoc_info->cesta_info->vcd_info[i].index;
-					entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[i]
-						.reg_value = cesta_vcd_curr_perfol_val;
-				}
+			for (i = 0; i < num_vcds; i++) {
+				vcd_idx = cesta_info->vcd_info[i].index;
+
+				cesta_vcd_curr_perfol_offset = vcd_curr_lvl_base +
+					(vcd_base_inc * vcd_idx);
+				cesta_vcd_curr_perfol_val =
+					cam_io_r_mb(cesta_base +
+					cesta_vcd_curr_perfol_offset);
+				entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[i].index =
+					cesta_info->vcd_info[i].index;
+				entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[i]
+					.reg_value = cesta_vcd_curr_perfol_val;
 			}
 			atomic_dec(&cpas_core->soc_access_count);
 			wake_up(&cpas_core->soc_access_count_wq);
 		}
 	}
 
-	for (i = 0; i < camnoc_info->specific_size; i++) {
-		if ((!camnoc_info->specific[i].enable) ||
-			(!camnoc_info->specific[i].maxwr_low.enable))
-			continue;
+	for (camnoc_idx = 0; camnoc_idx < cpas_core->num_valid_camnoc; camnoc_idx++) {
 
-		if (j >= CAM_CAMNOC_FILL_LVL_REG_INFO_MAX) {
-			CAM_WARN(CAM_CPAS,
-				"CPAS monitor reg info buffer full, max : %d",
-				j);
-			break;
+		camnoc_info = cpas_core->camnoc_info[camnoc_idx];
+		camnoc_reg_idx = cpas_core->regbase_index[camnoc_info->reg_base];
+
+		for (i = 0, j = 0; i < camnoc_info->specific_size; i++) {
+			if ((!camnoc_info->specific[i].enable) ||
+				(!camnoc_info->specific[i].maxwr_low.enable))
+				continue;
+
+			if (j >= CAM_CAMNOC_FILL_LVL_REG_INFO_MAX) {
+				CAM_WARN(CAM_CPAS,
+					"CPAS monitor reg info buffer full, max : %d",
+					j);
+				break;
+			}
+
+			entry->camnoc_port_name[camnoc_idx][j] =
+				camnoc_info->specific[i].port_name;
+			val = cam_io_r_mb(soc_info->reg_map[camnoc_reg_idx].mem_base +
+				camnoc_info->specific[i].maxwr_low.offset);
+			entry->camnoc_fill_level[camnoc_idx][j] = val;
+			j++;
 		}
 
-		entry->camnoc_port_name[j] = camnoc_info->specific[i].port_name;
-		val = cam_io_r_mb(soc_info->reg_map[reg_camnoc].mem_base +
-			camnoc_info->specific[i].maxwr_low.offset);
-		entry->camnoc_fill_level[j] = val;
-		j++;
+		entry->num_camnoc_lvl_regs[camnoc_idx] = j;
 	}
 
-	entry->num_camnoc_lvl_regs = j;
-
 	if (soc_private->enable_smart_qos) {
+
+		camnoc_info = cpas_core->camnoc_info[cpas_core->camnoc_rt_idx];
+		camnoc_reg_idx = cpas_core->regbase_index[camnoc_info->reg_base];
+
 		for (i = 0; i < soc_private->smart_qos_info->num_rt_wr_nius; i++) {
 			struct cam_cpas_tree_node *niu_node =
 				soc_private->smart_qos_info->rt_wr_niu_node[i];
 
 			entry->rt_wr_niu_pri_lut_high[i] =
-				cam_io_r_mb(soc_info->reg_map[reg_camnoc].mem_base +
+				cam_io_r_mb(soc_info->reg_map[camnoc_reg_idx].mem_base +
 					niu_node->pri_lut_high_offset);
 
 			entry->rt_wr_niu_pri_lut_low[i] =
-				cam_io_r_mb(soc_info->reg_map[reg_camnoc].mem_base +
+				cam_io_r_mb(soc_info->reg_map[camnoc_reg_idx].mem_base +
 					niu_node->pri_lut_low_offset);
 		}
 	}
@@ -3228,17 +3245,17 @@ static void cam_cpas_dump_monitor_array(
 	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
 	struct cam_cpas_private_soc *soc_private =
 		(struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
-	int i = 0, j = 0, k = 0;
+	int i = 0, k = 0;
 	int64_t state_head = 0;
-	uint32_t index, num_entries, oldest_entry;
+	uint32_t index, num_entries, oldest_entry, camnoc_idx, j;
 	uint64_t ms, hrs, min, sec;
 	struct cam_cpas_monitor *entry;
 	struct timespec64 curr_timestamp;
 	char log_buf[CAM_CPAS_LOG_BUF_LEN];
 	size_t len;
 	uint8_t vcd_index;
-	struct cam_camnoc_info *camnoc_info =
-		(struct cam_camnoc_info *) cpas_core->camnoc_info;
+	struct cam_cpas_cesta_info *cesta_info = cpas_core->cesta_info;
+	struct cam_camnoc_info *camnoc_info;
 
 	if (!cpas_core->full_state_dump)
 		return;
@@ -3315,36 +3332,45 @@ static void cam_cpas_dump_monitor_array(
 
 		if (cpas_core->regbase_index[CAM_CPAS_REG_CESTA] != -1) {
 			uint32_t vcd_base_inc =
-				camnoc_info->cesta_info->cesta_reg_info->vcd_currol.vcd_base_inc;
+				cesta_info->cesta_reg_info->vcd_currol.vcd_base_inc;
 			uint32_t vcd_curr_lvl_base =
-				camnoc_info->cesta_info->cesta_reg_info->vcd_currol.reg_offset;
+				cesta_info->cesta_reg_info->vcd_currol.reg_offset;
 			uint32_t reg_offset;
-			uint32_t num_vcds =
-				camnoc_info->cesta_info->cesta_reg_info->vcd_currol.num_vcds;
+			uint32_t num_vcds = cesta_info->num_vcds;
 
-			for (k = 0; k <= num_vcds; k++) {
-				reg_offset = vcd_curr_lvl_base + (vcd_base_inc * i);
+			for (k = 0; k < num_vcds; k++) {
 				vcd_index =
 					entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[k].index;
+				reg_offset = vcd_curr_lvl_base + (vcd_base_inc * vcd_index);
 				CAM_INFO(CAM_CPAS,
 					"VCD[index=%d, type=%d, name=%s] [offset=0x%x, value=0x%x]",
 					vcd_index,
-					camnoc_info->cesta_info->vcd_info[vcd_index].type,
-					camnoc_info->cesta_info->vcd_info[vcd_index].clk,
+					cesta_info->vcd_info[k].type,
+					cesta_info->vcd_info[k].clk,
 					reg_offset,
 					entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[k]
 					.reg_value);
 			}
 		}
 
-		for (j = 0; j < entry->num_camnoc_lvl_regs; j++) {
-			len += scnprintf((log_buf + len),
-				(CAM_CPAS_LOG_BUF_LEN - len), " %s:[%d %d]",
-				entry->camnoc_port_name[j],
-				(entry->camnoc_fill_level[j] & 0x7FF),
-				(entry->camnoc_fill_level[j] & 0x7F0000) >> 16);
+		for (camnoc_idx = 0; camnoc_idx < cpas_core->num_valid_camnoc; camnoc_idx++) {
+
+			camnoc_info = cpas_core->camnoc_info[camnoc_idx];
+			log_buf[0] = '\0';
+			len = 0;
+
+			for (j = 0; j < entry->num_camnoc_lvl_regs[camnoc_idx]; j++) {
+				len += scnprintf((log_buf + len),
+					(CAM_CPAS_LOG_BUF_LEN - len), " %s:[%d %d]",
+					entry->camnoc_port_name[camnoc_idx][j],
+					(entry->camnoc_fill_level[camnoc_idx][j] & 0x7FF),
+					(entry->camnoc_fill_level[camnoc_idx][j] & 0x7F0000)
+					>> 16);
+			}
+
+			CAM_INFO(CAM_CPAS, "%s REG[Queued Pending] %s",
+				camnoc_info->camnoc_name, log_buf);
 		}
-		CAM_INFO(CAM_CPAS, "CAMNOC REG[Queued Pending] %s", log_buf);
 
 		if (soc_private->enable_smart_qos) {
 			len = 0;

drivers/cam_cpas/cam_cpas_hw.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_CPAS_HW_H_
@@ -60,6 +60,20 @@
 	CAM_CPAS_MONITOR_MAX_ENTRIES, (ret))
 #define CAM_CPAS_MAX_CESTA_VCD_NUM 9
 
+/**
+ * enum cam_camnoc_domain_type - Enum for different camnoc domains
+ * @CAM_CAMNOC_HW_COMBINED: refer to legacy camnoc info that combines RT/NRT HW
+ * @CAM_CAMNOC_HW_RT: type for camnoc RT info
+ * @CAM_CAMNOC_HW_NRT: type for camnoc NRT info
+ * @CAM_CAMNOC_HW_TYPE_MAX: camnoc info maximum type
+ */
+enum cam_camnoc_hw_type {
+	CAM_CAMNOC_HW_COMBINED,
+	CAM_CAMNOC_HW_RT,
+	CAM_CAMNOC_HW_NRT,
+	CAM_CAMNOC_HW_TYPE_MAX,
+};
+
 /**
  * enum cam_cpas_access_type - Enum for Register access type
  */
@@ -322,9 +336,11 @@ struct cam_cpas_monitor {
 	uint32_t            fe_mnoc;
 	uint32_t            be_mnoc;
 	uint32_t            be_shub;
-	uint32_t            num_camnoc_lvl_regs;
-	const char          *camnoc_port_name[CAM_CAMNOC_FILL_LVL_REG_INFO_MAX];
-	uint32_t            camnoc_fill_level[CAM_CAMNOC_FILL_LVL_REG_INFO_MAX];
+	uint32_t            num_camnoc_lvl_regs[CAM_CAMNOC_HW_TYPE_MAX];
+	const char          *camnoc_port_name[CAM_CAMNOC_HW_TYPE_MAX]
+		[CAM_CAMNOC_FILL_LVL_REG_INFO_MAX];
+	uint32_t            camnoc_fill_level[CAM_CAMNOC_HW_TYPE_MAX]
+		[CAM_CAMNOC_FILL_LVL_REG_INFO_MAX];
 	uint32_t            rt_wr_niu_pri_lut_low[CAM_CPAS_MAX_RT_WR_NIU_NODES];
 	uint32_t            rt_wr_niu_pri_lut_high[CAM_CPAS_MAX_RT_WR_NIU_NODES];
 	struct cam_cpas_cesta_vcd_reg_debug_info vcd_reg_debug_info;
@@ -359,7 +375,11 @@ struct cam_cpas_monitor {
  * @applied_camnoc_axi_rate: applied camnoc axi clock rate through sw, hw clients
  * @monitor_head: Monitor array head
  * @monitor_entries: cpas monitor array
- * @camnoc_info: Pointer to camnoc header info
+ * @camnoc_info: array of camnoc info pointer
+ * @cesta_info: Pointer to cesta header info
+ * @num_valid_camnoc: number of valid camnoc info
+ * @camnoc_rt_idx: index to real time camnoc info array
+ * @camnoc_info_idx: map camnoc hw type to index used for camnoc_info array indexing
  * @full_state_dump: Whether to enable full cpas state dump or not
  * @smart_qos_dump: Whether to dump smart qos information on update
  * @slave_err_irq_en: Whether slave error irq is enabled to detect memory
@@ -378,7 +398,7 @@ struct cam_cpas {
 	uint32_t num_camnoc_axi_ports;
 	uint32_t registered_clients;
 	uint32_t streamon_clients;
-	uint32_t slave_err_irq_idx;
+	uint32_t slave_err_irq_idx[CAM_CAMNOC_HW_TYPE_MAX];
 	int32_t regbase_index[CAM_CPAS_REG_MAX];
 	struct cam_cpas_bus_client ahb_bus_client;
 	struct cam_cpas_axi_port axi_port[CAM_CPAS_MAX_AXI_PORTS];
@@ -392,10 +412,14 @@ struct cam_cpas {
 	struct cam_soc_util_clk_rates applied_camnoc_axi_rate;
 	atomic64_t  monitor_head;
 	struct cam_cpas_monitor monitor_entries[CAM_CPAS_MONITOR_MAX_ENTRIES];
-	void *camnoc_info;
+	void *camnoc_info[CAM_CAMNOC_HW_TYPE_MAX];
+	void *cesta_info;
+	uint8_t num_valid_camnoc;
+	int8_t camnoc_rt_idx;
+	int8_t camnoc_info_idx[CAM_CAMNOC_HW_TYPE_MAX];
 	bool full_state_dump;
 	bool smart_qos_dump;
-	bool slave_err_irq_en;
+	bool slave_err_irq_en[CAM_CAMNOC_HW_TYPE_MAX];
 	bool smmu_fault_handled;
 	bool force_hlos_drv;
 	bool force_cesta_sw_client;

drivers/cam_cpas/cam_cpas_hw_intf.h

@@ -42,6 +42,8 @@ enum cam_cpas_reg_base {
 	CAM_CPAS_REG_CAMSS,
 	CAM_CPAS_REG_RPMH,
 	CAM_CPAS_REG_CESTA,
+	CAM_CPAS_REG_CAMNOC_RT,
+	CAM_CPAS_REG_CAMNOC_NRT,
 	CAM_CPAS_REG_MAX
 };
 

drivers/cam_cpas/cam_cpas_soc.c

@@ -1699,10 +1699,37 @@ cleanup_clients:
 	return rc;
 }
 
+static int cam_cpas_soc_fill_irq_data(struct cam_hw_info *cpas_hw,
+	struct cam_hw_soc_info *soc_info, void **irq_data)
+{
+	struct cam_cpas_private_soc *soc_private = soc_info->soc_private;
+	int i;
+
+	for (i = 0; i < soc_info->irq_count; i++) {
+		soc_private->irq_data[i].cpas_hw = cpas_hw;
+
+		if (!strcmp(soc_info->irq_name[i], "cpas_camnoc"))
+			soc_private->irq_data[i].camnoc_type = CAM_CAMNOC_HW_COMBINED;
+		else if (!strcmp(soc_info->irq_name[i], "cpas_camnoc_rt"))
+			soc_private->irq_data[i].camnoc_type = CAM_CAMNOC_HW_RT;
+		else if (!strcmp(soc_info->irq_name[i], "cpas_camnoc_nrt"))
+			soc_private->irq_data[i].camnoc_type = CAM_CAMNOC_HW_NRT;
+		else {
+			CAM_ERR(CAM_CPAS, "Unable to identify interrupt name: %s",
+				soc_info->irq_name[i]);
+			return -EINVAL;
+		}
+
+		irq_data[i] = &soc_private->irq_data[i];
+	}
+
+	return 0;
+}
+
 int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info,
 	irq_handler_t irq_handler, struct cam_hw_info *cpas_hw)
 {
-	int rc = 0, i;
+	int rc = 0;
 	struct cam_cpas_private_soc *soc_private;
 	void *irq_data[CAM_SOC_MAX_IRQ_LINES_PER_DEV] = {0};
 
@@ -1717,30 +1744,38 @@ int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info,
 		return -EINVAL;
 	}
 
-	for (i = 0; i < soc_info->irq_count; i++)
-		irq_data[i] = cpas_hw;
+	soc_info->soc_private = kzalloc(sizeof(struct cam_cpas_private_soc),
+		GFP_KERNEL);
+	if (!soc_info->soc_private) {
+		CAM_ERR(CAM_CPAS, "Failed to allocate soc private");
+		return -ENOMEM;
+	}
+	soc_private = (struct cam_cpas_private_soc *)soc_info->soc_private;
 
-	rc = cam_soc_util_request_platform_resource(soc_info, irq_handler, &(irq_data[0]));
+	rc = cam_cpas_get_custom_dt_info(cpas_hw, soc_info->pdev, soc_private);
 	if (rc) {
-		CAM_ERR(CAM_CPAS, "failed in request_platform_resource, rc=%d",
-			rc);
-		return rc;
+		CAM_ERR(CAM_CPAS, "failed in get_custom_info, rc=%d", rc);
+		goto free_soc_private;
 	}
 
-	soc_info->soc_private = kzalloc(sizeof(struct cam_cpas_private_soc),
+	soc_private->irq_data = kcalloc(soc_info->irq_count, sizeof(struct cam_cpas_soc_irq_data),
 		GFP_KERNEL);
-	if (!soc_info->soc_private) {
+	if (!soc_private->irq_data) {
+		CAM_ERR(CAM_CPAS, "Failed to allocate irq data");
 		rc = -ENOMEM;
-		goto release_res;
+		goto free_soc_private;
 	}
 
-	soc_private = (struct cam_cpas_private_soc *)soc_info->soc_private;
+	rc = cam_cpas_soc_fill_irq_data(cpas_hw, soc_info, &(irq_data[0]));
+	if (rc) {
+		CAM_ERR(CAM_CPAS, "Failed to fill irq data rc=%d", rc);
+		goto free_irq_data;
+	}
 
-	rc = cam_cpas_get_custom_dt_info(cpas_hw, soc_info->pdev,
-		soc_info->soc_private);
+	rc = cam_soc_util_request_platform_resource(soc_info, irq_handler, &(irq_data[0]));
 	if (rc) {
-		CAM_ERR(CAM_CPAS, "failed in get_custom_info, rc=%d", rc);
-		goto free_soc_private;
+		CAM_ERR(CAM_CPAS, "failed in request_platform_resource, rc=%d", rc);
+		goto free_irq_data;
 	}
 
 	soc_info->is_clk_drv_en = soc_private->enable_cam_clk_drv;
@@ -1760,17 +1795,20 @@ int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info,
 		rc = cam_cpas_get_domain_id_support_clks(soc_info->pdev->dev.of_node,
 			soc_info, soc_private);
 		if (rc)
-			goto free_soc_private;
+			goto release_res;
 	}
 
 	return rc;
 
+release_res:
+	cam_soc_util_release_platform_resource(soc_info);
+free_irq_data:
+	kfree(soc_private->irq_data);
 free_soc_private:
 	kfree(soc_private->llcc_info);
 	kfree(soc_private->smart_qos_info);
 	kfree(soc_info->soc_private);
-release_res:
-	cam_soc_util_release_platform_resource(soc_info);
+	soc_info->soc_private = NULL;
 	return rc;
 }
 
@@ -1796,6 +1834,7 @@ int cam_cpas_soc_deinit_resources(struct cam_hw_soc_info *soc_info)
 	if (rc)
 		CAM_ERR(CAM_CPAS, "release platform failed, rc=%d", rc);
 
+	kfree(soc_private->irq_data);
 	kfree(soc_private->llcc_info);
 	kfree(soc_private->smart_qos_info);
 	kfree(soc_info->soc_private);

drivers/cam_cpas/cam_cpas_soc.h

@@ -203,6 +203,18 @@ struct cam_cpas_domain_id_support_clks {
 	int number_clks;
 };
 
+/**
+ * struct cam_cpas_soc_irq_data: irq data to be passed in irq handler from ISR
+ *
+ * @cpas_hw: cpas hw info
+ * @camnoc_type: type of camnoc associated with the irq
+ *
+ */
+struct cam_cpas_soc_irq_data {
+	struct cam_hw_info *cpas_hw;
+	enum cam_camnoc_hw_type camnoc_type;
+};
+
 /**
  * struct cam_cpas_private_soc : CPAS private DT info
  *
@@ -235,6 +247,7 @@ struct cam_cpas_domain_id_support_clks {
  * @icp_clk_index: Index of optional icp clk
  * @domain_id_info: Stores all information related to domain id support
  * @domain_id_clks: All clock related information for domain id support
+ * @irq_data: array of data for each irq line to be passed in irq handler
  */
 struct cam_cpas_private_soc {
 	const char *arch_compat;
@@ -264,6 +277,7 @@ struct cam_cpas_private_soc {
 	int32_t icp_clk_index;
 	struct cam_cpas_domain_id_info domain_id_info;
 	struct cam_cpas_domain_id_support_clks *domain_id_clks;
+	struct cam_cpas_soc_irq_data *irq_data;
 };
 
 void cam_cpas_dump_tree_vote_info(struct cam_hw_info *cpas_hw,

drivers/cam_cpas/cpas_top/cam_cpastop_hw.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_CPASTOP_HW_H_
@@ -63,6 +63,15 @@
  * @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR    : Triggered if any error
  *                                                   detected in the IPE/BPS
  *                                                   UBWC encoder instance
+ * @CAM_CAMNOC_HW_IRQ_OFE_UBWC_WRITE_ENCODE_ERROR  : Triggered if any error
+ *                                                   detected in the OFE write
+ *                                                   path enconder instance
+ * @CAM_CAMNOC_HW_IRQ_OFE_UBWC_READ_DECODE_ERROR   : Triggered if any error
+ *                                                   detected in the OFE read
+ *                                                   path enconder instance
+ * @CAM_CAMNOC_HW_IRQ_TFE_UBWC_ENCODE_ERROR        : Triggered if any error
+ *                                                   detected in the TFE
+ *                                                   UBWC enconder instance
  * @CAM_CAMNOC_HW_IRQ_RESERVED1                    : Reserved
  * @CAM_CAMNOC_HW_IRQ_RESERVED2                    : Reserved
  * @CAM_CAMNOC_HW_IRQ_CAMNOC_TEST                  : To test the IRQ logic
@@ -98,6 +107,12 @@ enum cam_camnoc_hw_irq_type {
 		CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
 	CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR =
 		CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
+	CAM_CAMNOC_HW_IRQ_OFE_UBWC_WRITE_ENCODE_ERROR =
+		CAM_CAMNOC_IRQ_OFE_WR_UBWC_ENCODE_ERROR,
+	CAM_CAMNOC_HW_IRQ_OFE_UBWC_READ_DECODE_ERROR =
+		CAM_CAMNOC_IRQ_OFE_RD_UBWC_DECODE_ERROR,
+	CAM_CAMNOC_HW_IRQ_TFE_UBWC_ENCODE_ERROR =
+		CAM_CAMNOC_IRQ_TFE_UBWC_ENCODE_ERROR,
 	CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT =
 		CAM_CAMNOC_IRQ_AHB_TIMEOUT,
 	CAM_CAMNOC_HW_IRQ_RESERVED1,
@@ -414,6 +429,9 @@ struct cam_cpas_cesta_info {
 /**
  * struct cam_camnoc_info : Overall CAMNOC settings info
  *
+ * @camnoc_type: type of camnoc (RT/NRT/COMBINED)
+ * @camnoc_name: name of camnoc (CAMNOC_RT/CAMNOC_NRT/CAMNOC_COMBINED)
+ * @reg_base: register base for camnoc RT/NRT/COMBINED register space
  * @specific: Pointer to CAMNOC SPECIFICTONTTPTR settings
  * @specific_size: Array size of SPECIFICTONTTPTR settings
  * @irq_sbm: Pointer to CAMNOC IRQ SBM settings
@@ -426,6 +444,12 @@ struct cam_cpas_cesta_info {
  *
  */
 struct cam_camnoc_info {
+	/* Below fields populated at probe on camera version */
+	enum cam_camnoc_hw_type camnoc_type;
+	char *camnoc_name;
+	enum cam_cpas_reg_base reg_base;
+
+	/* Below fields populated from the cpas header */
 	struct cam_camnoc_specific *specific;
 	int specific_size;
 	struct cam_camnoc_irq_sbm *irq_sbm;
@@ -440,6 +464,7 @@ struct cam_camnoc_info {
 /**
  * struct cam_cpas_work_payload : Struct for cpas work payload data
  *
+ * @camnoc_idx: index to camnoc info array
  * @hw: Pointer to HW info
  * @irq_status: IRQ status value
  * @irq_data: IRQ data
@@ -448,6 +473,7 @@ struct cam_camnoc_info {
  *
  */
 struct cam_cpas_work_payload {
+	int8_t camnoc_idx;
 	struct cam_hw_info *hw;
 	uint32_t irq_status;
 	uint32_t irq_data;

drivers/cam_cpas/cpas_top/cpastop_v880_100.h

@@ -1332,7 +1332,6 @@ static struct cam_camnoc_info cam880_cpas100_camnoc_info = {
 		.sbm_enable_mask = 0x80,
 		.sbm_clear_mask = 0x4,
 	},
-	.cesta_info = &cam_v880_cesta_info,
 };
 
 static struct cam_cpas_camnoc_qchannel cam880_cpas100_qchannel_info = {

drivers/cam_cpas/cpas_top/cpastop_v980_100.h

@@ -0,0 +1,1604 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CPASTOP_V980_100_H_
+#define _CPASTOP_V980_100_H_
+
+static struct cam_camnoc_irq_sbm cam_cpas_v980_100_irq_sbm_rt = {
+	.sbm_enable = {
+		.access_type = CAM_REG_TYPE_READ_WRITE,
+		.enable = true,
+		.offset = 0x240,  /* CAM_NOC_RT_SBM_FAULTINEN0_LOW */
+		.value = 0x01 |   /* RT_SBM_FAULTINEN0_LOW_PORT0_MASK - Slave error IRQ */
+			0x02,    /* RT_SBM_FAULTINEN0_LOW_PORT1_MASK - TFE UBWC Encoder Error IRQ */
+	},
+	.sbm_status = {
+		.access_type = CAM_REG_TYPE_READ,
+		.enable = true,
+		.offset = 0x248, /* CAM_NOC_RT_SBM_FAULTINSTATUS0_LOW */
+	},
+	.sbm_clear = {
+		.access_type = CAM_REG_TYPE_WRITE,
+		.enable = true,
+		.offset = 0x280, /* CAM_NOC_RT_SBM_FLAGOUTCLR0_LOW */
+		.value = 0x7,
+	}
+};
+
+static struct cam_camnoc_irq_sbm cam_cpas_v980_100_irq_sbm_nrt = {
+	.sbm_enable = {
+		.access_type = CAM_REG_TYPE_READ_WRITE,
+		.enable = true,
+		.offset = 0x240,  /* CAM_NOC_NRT_SBM_FAULTINEN0_LOW */
+		.value = 0x01 |   /* NRT_SBM_FAULTINEN0_LOW_PORT0_MASK - Slave Error */
+			0x02 |    /* NRT_SBM_FAULTINEN0_LOW_PORT1_MASK - IPE WR UBWC En */
+			0x04 |    /* NRT_SBM_FAULTINEN0_LOW_PORT2_MASK - OFE WR UBWC En */
+			0x08 |    /* NRT_SBM_FAULTINEN0_LOW_PORT3_MASK - OFE RD UBWC De */
+			0x10 |    /* NRT_SBM_FAULTINEN0_LOW_PORT4_MASK - IPE RD UBWC En */
+			0x20,     /* NRT_SBM_FAULTINEN0_LOW_PORT5_MASK - IPE RD UBWC En */
+	},
+	.sbm_status = {
+		.access_type = CAM_REG_TYPE_READ,
+		.enable = true,
+		.offset = 0x248, /* CAM_NOC_NRT_SBM_FAULTINSTATUS0_LOW */
+	},
+	.sbm_clear = {
+		.access_type = CAM_REG_TYPE_WRITE,
+		.enable = true,
+		.offset = 0x280, /* CAM_NOC_NRT_SBM_FLAGOUTCLR0_LOW */
+		.value = 0x7,
+	}
+};
+
+static struct cam_camnoc_irq_err
+	cam_cpas_v980_100_irq_err_rt[] = {
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
+		.enable = true,
+		.sbm_port = 0x1, /* RT_SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x8, /* CAM_NOC_RT_ERL_MAINCTL_LOW */
+			.value = 0x1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x10, /* CAM_NOC_RT_ERL_ERRVLD_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x18, /* CAM_NOC_RT_ERL_ERRCLR_LOW */
+			.value = 0x1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_TFE_UBWC_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x2, /* RT_SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x47A0, /* TFE_UBWC : RT_0_NIU_ENCERREN_LOW */
+			.value = 0xF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x4790, /* IFE_UBWC : RT_0_NIU_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x4798, /* IFE_UBWC : RT_0_NIU_ENCERRCLR_LOW */
+			.value = 0x1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
+		.enable = false,
+		.sbm_port = 0x20, /* RT_SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x288, /* RT_CAM_NOC_RT_SBM_FLAGOUTSET0_LOW */
+			.value = 0x1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x290, /* CAM_NOC_RT_SBM_FLAGOUTSTATUS0_LOW */
+		},
+		.err_clear = {
+			.enable = false, /* CAM_NOC_RT_SBM_FLAGOUTCLR0_LOW */
+		},
+	},
+};
+
+static struct cam_camnoc_irq_err
+	cam_cpas_v980_100_irq_err_nrt[] = {
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
+		.enable = true,
+		.sbm_port = 0x1, /* NRT_SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x8, /* CAM_NOC_NRT_ERL_MAINCTL_LOW */
+			.value = 0x1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x10, /* CAM_NOC_NRT_ERL_ERRVLD_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x18, /* CAM_NOC_NRT_ERL_ERRCLR_LOW */
+			.value = 0x1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_OFE_UBWC_WRITE_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x4, /* NRT_SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x63A0, /* OFE_WR : NRT_3_NIU_ENCERREN_LOW */
+			.value = 0xF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x6390, /* OFE_WR : NRT_3_NIU_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x6398, /* OFE_WR : NRT_3_NIU_ENCERRCLR_LOW */
+			.value = 0x1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_OFE_UBWC_READ_DECODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x8, /* NRT_SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x6520, /* OFE_RD : NRT_4_NIU_DECERREN_LOW */
+			.value = 0xFF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x6510, /* OFE_RD : NRT_4_NIU_DECERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x6518, /* OFE_RD : NRT_4_NIU_DECERRCLR_LOW */
+			.value = 0x1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x2, /* NRT_SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x59A0, /* IPE_WR : NRT_1_NIU_ENCERREN_LOW */
+			.value = 0xF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x5990, /* IPE_WR : NRT_1_NIU_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x5998, /* IPE_WR : NRT_1_NIU_ENCERRCLR_LOW */
+			.value = 0x1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x20, /* NRT_SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x6D20, /* IPE_0_RD : NRT_8_NIU_DECERREN_LOW */
+			.value = 0xFF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x6D10, /* IPE_0_RD : NRT_8_NIU_DECERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x6D18, /* IPE_0_RD : NRT_8_NIU_DECERRCLR_LOW */
+			.value = 0x1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE1_UBWC_DECODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x10, /* NRT_SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x6B20, /* IPE_1_RD : NRT_7_NIU_DECERREN_LOW */
+			.value = 0xFF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x6B10, /* IPE_1_RD : NRT_7_NIU_DECERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x6B18, /* IPE_1_RD : NRT_7_NIU_DECERRCLR_LOW */
+			.value = 0xFF,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
+		.enable = false,
+		.sbm_port = 0x40, /* NRT_SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x288, /* CAM_NOC_NRT_SBM_FLAGOUTSET0_LOW */
+			.value = 0xE,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x290, /* CAM_NOC_NRT_SBM_FLAGOUTSTATUS0_LOW */
+		},
+		.err_clear = {
+			.enable = false, /* CAM_NOC_NRT_SBM_FLAGOUTCLR0_LOW */
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
+		.enable = false,
+		.sbm_port = 0x400, /* NRT_SBM_FAULTINSTATUS0_LOW_PORT10_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x288, /* CAM_NOC_NRT_SBM_FLAGOUTSET0_LOW */
+			.value = 0x2,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x290, /* CAM_NOC_NRT_SBM_FLAGOUTSTATUS0_LOW */
+		},
+		.err_clear = {
+			.enable = false, /* CAM_NOC_NRT_SBM_FLAGOUTCLR0_LOW */
+		},
+	},
+};
+
+static struct cam_camnoc_specific
+	cam_cpas_v980_100_camnoc_specific_rt[] = {
+	/* RT ports */
+	{
+		.port_name = "RT0-TFE_LINEAR_RDI",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_0_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_0_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_0_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_0_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_0_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_0_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_0_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_0_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_0_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "RT1-TFE_FD_PDAF_IFE_LITE",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_FD_PDAF_IFE_LITE : NOC_RT_1_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "RT2-TFE_STATS",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_STATS : NOC_RT_2_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "RT3-TFE_IFE_LITE_CDM",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_IFE_LITE_CDM : NOC_RT_3_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "RT4-TFE_LINEAR_RDI",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* TFE_LINEAR_RDI : NOC_RT_4_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+};
+
+static struct cam_camnoc_specific
+	cam_cpas_v980_100_camnoc_specific_nrt[] = {
+	/* NRT ports */
+	{
+		.port_name = "NRT0-IPE_WR_1",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_0_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_0_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_0_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_0_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_0_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_0_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_0_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_0_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_0_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "NRT1-IPE_WR_0",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_0 : NOC_NRT_1_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "NRT2-OFE_WR_1-CRE_WR",
+		.enable = false,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_BPS_WR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_1-CRE_WR : NOC_NRT_2_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "NRT3-OFE_WR_0",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_0 : NOC_NRT_3_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_0 : NOC_NRT_3_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_0 : NOC_NRT_3_NIU_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_0 : NOC_NRT_3_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_0 : NOC_NRT_3_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_0 : NOC_NRT_3_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_0 : NOC_NRT_3_QOSGEN_MAINCTL */
+			.value = 0x2,
+		},
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_0 : NOC_NRT_3_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_WR_0 : NOC_NRT_3_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "NRT4-OFE_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_NIU_DECCTL_LOW */
+			.value = 1,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* OFE_RD : NOC_NRT_4_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "NRT5-CRE_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CRE_RD : NOC_NRT_5_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CRE_RD : NOC_NRT_5_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CRE_RD : NOC_NRT_5_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CRE_RD : NOC_NRT_5_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CRE_RD : NOC_NRT_5_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CRE_RD : NOC_NRT_5_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CRE_RD : NOC_NRT_5_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CRE_RD : NOC_NRT_5_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CRE_RD : NOC_NRT_5_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "NRT6-JPEG_RD_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* JPEG_RD_WR : NOC_NRT_6_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "NRT7-IPE_WR_1",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_WR_1 : NOC_NRT_7_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "NRT8-IPE_RD_0",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* IPE_RD_0 : NOC_NRT_8_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "NRT9-CDM_IPE_OFE",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_NIU_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_NIU_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_NIU_URGENCY_LOW */
+			.value = 0x0,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_NIU_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_NIU_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.dynattr_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x0, /* CDM_IPE_OFE : NOC_NRT_9_NIU_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_name = "ICP_RD_WR",
+		.enable = false,
+		.dynattr_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* ICP_RD_WR : NOC_XM_ICP_DYNATTR_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* ICP_RD_WR : NOC_XM_ICP_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* ICP_RD_WR : NOC_XM_ICP_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x0, /* ICP_RD_WR : NOC_XM_ICP_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+};
+
+static struct cam_camnoc_err_logger_info cam980_cpas100_err_logger_offsets = {
+	.mainctrl     =  0x08, /* NOC_ERL_MAINCTL_LOW */
+	.errvld       =  0x10, /* NOC_ERL_ERRVLD_LOW */
+	.errlog0_low  =  0x20, /* NOC_ERL_ERRLOG0_LOW */
+	.errlog0_high =  0x24, /* NOC_ERL_ERRLOG0_HIGH */
+	.errlog1_low  =  0x28, /* NOC_ERL_ERRLOG1_LOW */
+	.errlog1_high =  0x2C, /* NOC_ERL_ERRLOG1_HIGH */
+	.errlog2_low  =  0x30, /* NOC_ERL_ERRLOG2_LOW */
+	.errlog2_high =  0x34, /* NOC_ERL_ERRLOG2_HIGH */
+	.errlog3_low  =  0x38, /* NOC_ERL_ERRLOG3_LOW */
+	.errlog3_high =  0x3C, /* NOC_ERL_ERRLOG3_HIGH */
+};
+
+static struct cam_cpas_hw_errata_wa_list cam980_cpas100_errata_wa_list = {
+	.camnoc_flush_slave_pending_trans = {
+		.enable = false,
+		.data.reg_info = {
+			.access_type = CAM_REG_TYPE_READ,
+			.offset = 0x300, /* sbm_SenseIn0_Low */
+			.mask = 0xE0000, /* Bits 17, 18, 19 */
+			.value = 0, /* expected to be 0 */
+		},
+	},
+	.enable_icp_clk_for_qchannel = {
+		.enable = false,
+	},
+};
+
+static struct cam_cpas_cesta_vcd_reg_info cam_cpas_v980_100_cesta_reg_info = {
+	.vcd_currol = {
+		.reg_offset = 0x266C,
+		.vcd_base_inc = 0x210,
+		.num_vcds = 8,
+	},
+};
+
+static struct cam_cpas_vcd_info cam_v980_100_vcd_info[] = {
+	{
+		.index = 0, .type = CAM_CESTA_CRMC, .clk = "cam_cc_tfe_0_clk_src",
+	},
+	{
+		.index = 1, .type = CAM_CESTA_CRMC, .clk = "cam_cc_tfe_1_clk_src",
+	},
+	{
+		.index = 2, .type = CAM_CESTA_CRMC, .clk = "cam_cc_tfe_2_clk_src",
+	},
+	{
+		.index = 6, .type = CAM_CESTA_CRMC, .clk = "cam_cc_csid_clk_src",
+	},
+	{
+		.index = 7, .type = CAM_CESTA_CRMC, .clk = "cam_cc_cphy_rx_clk_src",
+	},
+	{
+		.index = 8, .type = CAM_CESTA_CRMB, .clk = "cam_cc_camnoc_axi_rt_clk_src",
+	},
+};
+
+static struct cam_cpas_cesta_info cam_v980_cesta_info = {
+	 .vcd_info = &cam_v980_100_vcd_info[0],
+	 .num_vcds = ARRAY_SIZE(cam_v980_100_vcd_info),
+	 .cesta_reg_info = &cam_cpas_v980_100_cesta_reg_info,
+};
+
+static struct cam_camnoc_info cam980_cpas100_camnoc_info_rt = {
+	.specific = &cam_cpas_v980_100_camnoc_specific_rt[0],
+	.specific_size = ARRAY_SIZE(cam_cpas_v980_100_camnoc_specific_rt),
+	.irq_sbm = &cam_cpas_v980_100_irq_sbm_rt,
+	.irq_err = &cam_cpas_v980_100_irq_err_rt[0],
+	.irq_err_size = ARRAY_SIZE(cam_cpas_v980_100_irq_err_rt),
+	.err_logger = &cam980_cpas100_err_logger_offsets,
+	.errata_wa_list = &cam980_cpas100_errata_wa_list,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x20,
+		.sbm_clear_mask = 0x4,
+	},
+};
+
+static struct cam_camnoc_info cam980_cpas100_camnoc_info_nrt = {
+	.specific = &cam_cpas_v980_100_camnoc_specific_nrt[0],
+	.specific_size = ARRAY_SIZE(cam_cpas_v980_100_camnoc_specific_nrt),
+	.irq_sbm = &cam_cpas_v980_100_irq_sbm_nrt,
+	.irq_err = &cam_cpas_v980_100_irq_err_nrt[0],
+	.irq_err_size = ARRAY_SIZE(cam_cpas_v980_100_irq_err_nrt),
+	.err_logger = &cam980_cpas100_err_logger_offsets,
+	.errata_wa_list = &cam980_cpas100_errata_wa_list,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x400,
+		.sbm_clear_mask = 0x1,
+	},
+};
+
+static struct cam_cpas_camnoc_qchannel cam980_cpas100_qchannel_info_rt = {
+	.qchannel_ctrl   = 0xEC,
+	.qchannel_status = 0xF0,
+};
+
+static struct cam_cpas_camnoc_qchannel cam980_cpas100_qchannel_info_nrt = {
+	.qchannel_ctrl   = 0xF4,
+	.qchannel_status = 0xF8,
+};
+#endif /* _CPASTOP_V980_100_H_ */

drivers/cam_cpas/include/cam_cpas_api.h

@@ -83,7 +83,8 @@ enum cam_cpas_camera_version {
 	CAM_CPAS_CAMERA_VERSION_165  = 0x00010605,
 	CAM_CPAS_CAMERA_VERSION_780  = 0x00070800,
 	CAM_CPAS_CAMERA_VERSION_640  = 0x00060400,
-	CAM_CPAS_CAMERA_VERSION_880 =  0x00080800,
+	CAM_CPAS_CAMERA_VERSION_880  = 0x00080800,
+	CAM_CPAS_CAMERA_VERSION_980  = 0x00090800,
 	CAM_CPAS_CAMERA_VERSION_MAX
 };
 
@@ -119,7 +120,8 @@ enum cam_cpas_camera_version_map_id {
 	CAM_CPAS_CAMERA_VERSION_ID_165  = 0xA,
 	CAM_CPAS_CAMERA_VERSION_ID_780  = 0xB,
 	CAM_CPAS_CAMERA_VERSION_ID_640  = 0xC,
-	CAM_CPAS_CAMERA_VERSION_ID_880 =  0xD,
+	CAM_CPAS_CAMERA_VERSION_ID_880  = 0xD,
+	CAM_CPAS_CAMERA_VERSION_ID_980  = 0xE,
 	CAM_CPAS_CAMERA_VERSION_ID_MAX
 };
 
@@ -164,6 +166,7 @@ enum cam_cpas_hw_version {
 	CAM_CPAS_TITAN_780_V100 = 0x780100,
 	CAM_CPAS_TITAN_640_V200 = 0x640200,
 	CAM_CPAS_TITAN_880_V100 = 0x880100,
+	CAM_CPAS_TITAN_980_V100 = 0x980100,
 	CAM_CPAS_TITAN_MAX
 };
 
@@ -226,12 +229,15 @@ enum cam_camnoc_slave_error_codes {
  * @CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: Triggered if any error detected
  *                                            in the IPE/BPS UBWC encoder
  *                                            instance
- * @CAM_CAMNOC_IRQ_OFE_WR_UBWC_DECODE_ERROR : Triggered if any error detected
+ * @CAM_CAMNOC_IRQ_OFE_WR_UBWC_ENCODE_ERROR : Triggered if any error detected
  *                                            in the OFE write UBWC decoder
  *                                            instance
  * @CAM_CAMNOC_IRQ_OFE_RD_UBWC_DECODE_ERROR : Triggered if any error detected
  *                                            in the OFE read UBWC decoder
  *                                            instance
+ * @CAM_CAMNOC_IRQ_TFE_UBWC_ENCODE_ERROR    : Triggered if any error detected
+ *                                            in the TFE UBWC encoder
+ *                                            instance
  * @CAM_CAMNOC_IRQ_AHB_TIMEOUT              : Triggered when the QHS_ICP slave
  *                                            times out after 4000 AHB cycles
  */
@@ -251,8 +257,9 @@ enum cam_camnoc_irq_type {
 	CAM_CAMNOC_IRQ_IPE1_UBWC_DECODE_ERROR,
 	CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
 	CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
-	CAM_CAMNOC_IRQ_OFE_WR_UBWC_DECODE_ERROR,
+	CAM_CAMNOC_IRQ_OFE_WR_UBWC_ENCODE_ERROR,
 	CAM_CAMNOC_IRQ_OFE_RD_UBWC_DECODE_ERROR,
+	CAM_CAMNOC_IRQ_TFE_UBWC_ENCODE_ERROR,
 	CAM_CAMNOC_IRQ_AHB_TIMEOUT,
 };
 

drivers/cam_icp/icp_hw/ofe_hw/ofe_dev.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -41,7 +41,7 @@ static bool cam_ofe_cpas_cb(uint32_t client_handle, void *userdata,
 		return error_handled;
 
 	switch (irq_data->irq_type) {
-	case CAM_CAMNOC_IRQ_OFE_WR_UBWC_DECODE_ERROR:
+	case CAM_CAMNOC_IRQ_OFE_WR_UBWC_ENCODE_ERROR:
 		CAM_ERR_RATE_LIMIT(CAM_ICP,
 			"OFE Write UBWC Decode error type=%d status=%x thr_err=%d, fcl_err=%d, len_md_err=%d, format_err=%d",
 			irq_data->irq_type,

drivers/cam_utils/cam_soc_util.c

@@ -2911,7 +2911,7 @@ int cam_soc_util_request_platform_resource(
 		return -EINVAL;
 	}
 
-	if (unlikely(soc_info->irq_count >= CAM_SOC_MAX_IRQ_LINES_PER_DEV)) {
+	if (unlikely(soc_info->irq_count > CAM_SOC_MAX_IRQ_LINES_PER_DEV)) {
 		CAM_ERR(CAM_UTIL, "Invalid irq count: %u Max IRQ per device: %d",
 			soc_info->irq_count, CAM_SOC_MAX_IRQ_LINES_PER_DEV);
 		return -EINVAL;