qcacmn: Add hal_rx_desc_is_first_msdu API
Implement hal_rx_desc_is_first_msdu API based on the chipset as the macro to retrieve first_msdu bit value is chipset dependent. Change-Id: I8e8a3aceb225b591b96e6f8453ffbebf1f78e529 CRs-Fixed: 2522133
This commit is contained in:

committed by
nshrivas

parent
5bf1e5a1da
commit
43d563277d
@@ -731,7 +731,7 @@ uint8_t dp_rx_process_invalid_peer(struct dp_soc *soc, qdf_nbuf_t mpdu,
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rx_pkt_hdr = hal_rx_pkt_hdr_get(rx_tlv_hdr);
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if (!HAL_IS_DECAP_FORMAT_RAW(rx_tlv_hdr)) {
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if (!HAL_IS_DECAP_FORMAT_RAW(soc->hal_soc, rx_tlv_hdr)) {
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QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
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"Drop decapped frames");
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goto free;
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@@ -415,7 +415,8 @@ dp_rx_mon_mpdu_pop(struct dp_soc *soc, uint32_t mac_id,
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buf_info.paddr;
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}
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if (hal_rx_desc_is_first_msdu(rx_desc_tlv))
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if (hal_rx_desc_is_first_msdu(soc->hal_soc,
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rx_desc_tlv))
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hal_rx_mon_hw_desc_get_mpdu_status(soc->hal_soc,
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rx_desc_tlv,
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&(dp_pdev->ppdu_info.rx_status));
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@@ -384,6 +384,7 @@ struct hal_hw_txrx_ops {
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uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
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uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf);
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uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf);
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uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr);
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};
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/**
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@@ -3389,13 +3389,21 @@ void hal_reo_status_get_header(uint32_t *d, int b,
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hal_soc->ops->hal_reo_status_get_header(d, b, h);
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}
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/**
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* hal_rx_desc_is_first_msdu() - Check if first msdu
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*
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* @hal_soc_hdl: hal_soc handle
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* @hw_desc_addr: hardware descriptor address
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*
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* Return: 0 - success/ non-zero failure
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*/
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static inline
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uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr)
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uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl,
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void *hw_desc_addr)
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{
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struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
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struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
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return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr);
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}
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static inline
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@@ -3433,11 +3441,12 @@ HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
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#ifdef NO_RX_PKT_HDR_TLV
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static inline
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bool HAL_IS_DECAP_FORMAT_RAW(uint8_t *rx_tlv_hdr)
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bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl,
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uint8_t *rx_tlv_hdr)
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{
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uint8_t decap_format;
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if (hal_rx_desc_is_first_msdu(rx_tlv_hdr)) {
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if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) {
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decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr);
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if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW)
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return true;
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@@ -3447,7 +3456,8 @@ bool HAL_IS_DECAP_FORMAT_RAW(uint8_t *rx_tlv_hdr)
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}
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#else
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static inline
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bool HAL_IS_DECAP_FORMAT_RAW(uint8_t *rx_tlv_hdr)
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bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl,
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uint8_t *rx_tlv_hdr)
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{
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return true;
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}
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@@ -181,6 +181,22 @@ uint16_t hal_rx_msdu_end_sa_idx_get_6290(uint8_t *buf)
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return sa_idx;
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}
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/**
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* hal_rx_desc_is_first_msdu_6290() - Check if first msdu
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*
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* @hal_soc_hdl: hal_soc handle
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* @hw_desc_addr: hardware descriptor address
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*
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* Return: 0 - success/ non-zero failure
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*/
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static uint32_t hal_rx_desc_is_first_msdu_6290(void *hw_desc_addr)
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{
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struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
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struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
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return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
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}
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struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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@@ -226,6 +242,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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hal_rx_msdu_end_da_is_mcbc_get_6290,
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hal_rx_msdu_end_sa_is_valid_get_6290,
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hal_rx_msdu_end_sa_idx_get_6290,
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hal_rx_desc_is_first_msdu_6290,
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};
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struct hal_hw_srng_config hw_srng_table_6290[] = {
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@@ -180,6 +180,23 @@ uint16_t hal_rx_msdu_end_sa_idx_get_6390(uint8_t *buf)
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return sa_idx;
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}
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/**
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* hal_rx_desc_is_first_msdu_6390() - Check if first msdu
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*
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* @hal_soc_hdl: hal_soc handle
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* @hw_desc_addr: hardware descriptor address
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*
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* Return: 0 - success/ non-zero failure
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*/
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static uint32_t hal_rx_desc_is_first_msdu_6390(void *hw_desc_addr)
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{
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struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
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struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
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return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
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}
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struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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@@ -225,6 +242,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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hal_rx_msdu_end_da_is_mcbc_get_6390,
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hal_rx_msdu_end_sa_is_valid_get_6390,
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hal_rx_msdu_end_sa_idx_get_6390,
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hal_rx_desc_is_first_msdu_6390,
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};
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struct hal_hw_srng_config hw_srng_table_6390[] = {
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@@ -87,9 +87,26 @@ uint16_t hal_rx_msdu_end_sa_idx_get_6490(uint8_t *buf)
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return sa_idx;
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}
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/**
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* hal_rx_desc_is_first_msdu_6490() - Check if first msdu
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*
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* @hal_soc_hdl: hal_soc handle
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* @hw_desc_addr: hardware descriptor address
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*
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* Return: 0 - success/ non-zero failure
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*/
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static uint32_t hal_rx_desc_is_first_msdu_6490(void *hw_desc_addr)
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{
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struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
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struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
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return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU);
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}
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struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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/* rx */
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hal_rx_get_rx_fragment_number_6490,
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hal_rx_msdu_end_da_is_mcbc_get_6490,
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hal_rx_msdu_end_sa_is_valid_get_6490,
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hal_rx_desc_is_first_msdu_6490,
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};
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@@ -176,6 +176,21 @@ static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf)
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return sa_idx;
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}
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/**
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* hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu
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*
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* @hal_soc_hdl: hal_soc handle
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* @hw_desc_addr: hardware descriptor address
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*
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* Return: 0 - success/ non-zero failure
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*/
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static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr)
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{
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struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
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struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
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return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
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}
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struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
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/* init and setup */
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@@ -222,6 +237,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
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hal_rx_msdu_end_da_is_mcbc_get_8074v1,
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hal_rx_msdu_end_sa_is_valid_get_8074v1,
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hal_rx_msdu_end_sa_idx_get_8074v1,
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hal_rx_desc_is_first_msdu_8074v1,
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};
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struct hal_hw_srng_config hw_srng_table_8074[] = {
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@@ -176,6 +176,22 @@ static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf)
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return sa_idx;
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}
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/**
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* hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu
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*
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* @hal_soc_hdl: hal_soc handle
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* @hw_desc_addr: hardware descriptor address
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*
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* Return: 0 - success/ non-zero failure
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*/
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static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr)
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{
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struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
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struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
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return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
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}
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struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
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/* init and setup */
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@@ -222,6 +238,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
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hal_rx_msdu_end_da_is_mcbc_get_8074v2,
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hal_rx_msdu_end_sa_is_valid_get_8074v2,
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hal_rx_msdu_end_sa_idx_get_8074v2,
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hal_rx_desc_is_first_msdu_8074v2,
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};
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struct hal_hw_srng_config hw_srng_table_8074v2[] = {
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@@ -185,6 +185,22 @@ static uint16_t hal_rx_msdu_end_sa_idx_get_9000(uint8_t *buf)
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return sa_idx;
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}
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/**
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* hal_rx_desc_is_first_msdu_9000() - Check if first msdu
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*
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* @hal_soc_hdl: hal_soc handle
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* @hw_desc_addr: hardware descriptor address
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*
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* Return: 0 - success/ non-zero failure
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*/
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static uint32_t hal_rx_desc_is_first_msdu_9000(void *hw_desc_addr)
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{
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struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
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struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
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return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
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}
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struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
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/* init and setup */
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@@ -231,6 +247,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
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hal_rx_msdu_end_da_is_mcbc_get_9000,
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hal_rx_msdu_end_sa_is_valid_get_9000,
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hal_rx_msdu_end_sa_idx_get_9000,
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hal_rx_desc_is_first_msdu_9000,
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};
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struct hal_hw_srng_config hw_srng_table_9000[] = {
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