ipahal: Add support for general resource configs

Add infrastructure to configure the following registers:
IPA_RSRC_GRP_CFG
IPA_RSRC_GRP_CFG_EXT

Add global hardcoded configuration matrix.
Add configuration at init.

Change-Id: I9ec78e2aef69f1bccafe620addc00e600687fa17
Signed-off-by: Ilia Lin <[email protected]>

drivers/platform/msm/ipa/ipa_v3/ipa.c

@@ -7399,6 +7399,9 @@ static int ipa3_post_init(const struct ipa3_plat_drv_res *resource_p,
 	/* Assign resource limitation to each group */
 	ipa3_set_resorce_groups_min_max_limits();
 
+	/* Initialize general resource group parameters */
+	ipa3_set_resorce_groups_config();
+
 	idr = &(ipa3_ctx->flt_rule_ids[IPA_IP_v4]);
 	idr_init(idr);
 	idr = &(ipa3_ctx->flt_rule_ids[IPA_IP_v6]);

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

@@ -3320,6 +3320,7 @@ int ipa3_create_wdi_mapping(u32 num_buffers, struct ipa_wdi_buffer_info *info);
 int ipa3_set_flt_tuple_mask(int pipe_idx, struct ipahal_reg_hash_tuple *tuple);
 int ipa3_set_rt_tuple_mask(int tbl_idx, struct ipahal_reg_hash_tuple *tuple);
 void ipa3_set_resorce_groups_min_max_limits(void);
+void ipa3_set_resorce_groups_config(void);
 int ipa3_suspend_apps_pipes(bool suspend);
 void ipa3_force_close_coal(void);
 int ipa3_flt_read_tbl_from_hw(u32 pipe_idx,

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

@@ -276,6 +276,17 @@ struct rsrc_min_max {
 	u32 max;
 };
 
+struct ipa_rsrc_cfg {
+	u8 src_grp_index;
+	bool src_grp_valid;
+	u8 dst_pipe_index;
+	bool dst_pipe_valid;
+	u8 dst_grp_index;
+	bool dst_grp_valid;
+	u8 src_grp_2nd_prio_index;
+	bool src_grp_2nd_prio_valid;
+};
+
 enum ipa_ver {
 	IPA_3_0,
 	IPA_3_5,
@@ -867,6 +878,28 @@ static const u32 ipa3_rsrc_rx_grp_hps_weight_config
 	},
 };
 
+static const struct ipa_rsrc_cfg ipa_rsrc_config[IPA_VER_MAX] = {
+	[IPA_5_0] = {
+		.src_grp_index          = 4,
+		.src_grp_valid          = 1,
+		.dst_pipe_index         = 0,
+		.dst_pipe_valid         = 0,
+		.dst_grp_index          = 0,
+		.dst_grp_valid          = 0,
+		.src_grp_2nd_prio_index = 1,
+		.src_grp_2nd_prio_valid = 1,
+	},
+	[IPA_5_1] = {
+		.src_grp_index          = 4,
+		.src_grp_valid          = 1,
+		.dst_pipe_index         = 0,
+		.dst_pipe_valid         = 0,
+		.dst_grp_index          = 0,
+		.dst_grp_valid          = 0,
+		.src_grp_2nd_prio_index = 1,
+		.src_grp_2nd_prio_valid = 1,
+	},
+};
 
 enum ipa_qmb_instance_type {
 	IPA_QMB_INSTANCE_DDR = 0,
@@ -10185,7 +10218,7 @@ bool ipa_is_modem_pipe(int pipe_idx)
 
 static void ipa3_write_rsrc_grp_type_reg(int group_index,
 			enum ipa_rsrc_grp_type_src n, bool src,
-			struct ipahal_reg_rsrc_grp_cfg *val)
+			struct ipahal_reg_rsrc_grp_xy_cfg *val)
 {
 	u8 hw_type_idx;
 
@@ -10699,7 +10732,7 @@ void ipa3_set_resorce_groups_min_max_limits(void)
 	int dst_rsrc_type_max;
 	int src_grp_idx_max;
 	int dst_grp_idx_max;
-	struct ipahal_reg_rsrc_grp_cfg val;
+	struct ipahal_reg_rsrc_grp_xy_cfg val;
 	u8 hw_type_idx;
 
 	IPADBG("ENTER\n");
@@ -10829,6 +10862,31 @@ void ipa3_set_resorce_groups_min_max_limits(void)
 	IPADBG("EXIT\n");
 }
 
+void ipa3_set_resorce_groups_config(void)
+{
+	struct ipahal_reg_rsrc_grp_cfg cfg;
+	struct ipahal_reg_rsrc_grp_cfg_ext cfg_ext;
+
+	IPADBG("ENTER\n");
+
+	if (ipa3_ctx->ipa_hw_type >= IPA_HW_v5_0) {
+		cfg.src_grp_index = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_index;
+		cfg.src_grp_valid = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_valid;
+		cfg.dst_pipe_index = ipa_rsrc_config[ipa3_ctx->hw_type_index].dst_pipe_index;
+		cfg.dst_pipe_valid = ipa_rsrc_config[ipa3_ctx->hw_type_index].dst_pipe_valid;
+		cfg.dst_grp_index = ipa_rsrc_config[ipa3_ctx->hw_type_index].dst_grp_index;
+		cfg.src_grp_valid = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_valid;
+		cfg_ext.index = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_2nd_prio_index;
+		cfg_ext.valid = ipa_rsrc_config[ipa3_ctx->hw_type_index].src_grp_2nd_prio_valid;
+
+		IPADBG("Write IPA_RSRC_GRP_CFG\n");
+		ipahal_write_reg_fields(IPA_RSRC_GRP_CFG, &cfg);
+		IPADBG("Write IPA_RSRC_GRP_CFG_EXT\n");
+		ipahal_write_reg_fields(IPA_RSRC_GRP_CFG_EXT, &cfg_ext);
+	}
+	IPADBG("EXIT\n");
+}
+
 static void ipa3_gsi_poll_after_suspend(struct ipa3_ep_context *ep)
 {
 	bool empty;

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

@@ -101,6 +101,8 @@ static const char *ipareg_name_to_str[IPA_REG_MAX] = {
 	__stringify(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n),
 	__stringify(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n),
 	__stringify(IPA_DST_RSRC_GRP_67_RSRC_TYPE_n),
+	__stringify(IPA_RSRC_GRP_CFG),
+	__stringify(IPA_RSRC_GRP_CFG_EXT),
 	__stringify(IPA_RX_HPS_CLIENTS_MIN_DEPTH_0),
 	__stringify(IPA_RX_HPS_CLIENTS_MIN_DEPTH_1),
 	__stringify(IPA_RX_HPS_CLIENTS_MAX_DEPTH_0),
@@ -275,8 +277,8 @@ static void ipareg_construct_rx_hps_clients_depth0_v4_5(
 static void ipareg_construct_rsrg_grp_xy(
 	enum ipahal_reg_name reg, const void *fields, u32 *val)
 {
-	struct ipahal_reg_rsrc_grp_cfg *grp =
-		(struct ipahal_reg_rsrc_grp_cfg *)fields;
+	struct ipahal_reg_rsrc_grp_xy_cfg *grp =
+		(struct ipahal_reg_rsrc_grp_xy_cfg *)fields;
 
 	IPA_SETFIELD_IN_REG(*val, grp->x_min,
 		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT,
@@ -295,8 +297,8 @@ static void ipareg_construct_rsrg_grp_xy(
 static void ipareg_construct_rsrg_grp_xy_v3_5(
 	enum ipahal_reg_name reg, const void *fields, u32 *val)
 {
-	struct ipahal_reg_rsrc_grp_cfg *grp =
-		(struct ipahal_reg_rsrc_grp_cfg *)fields;
+	struct ipahal_reg_rsrc_grp_xy_cfg *grp =
+		(struct ipahal_reg_rsrc_grp_xy_cfg *)fields;
 
 	IPA_SETFIELD_IN_REG(*val, grp->x_min,
 		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5,
@@ -320,8 +322,8 @@ static void ipareg_construct_rsrg_grp_xy_v3_5(
 static void ipareg_construct_rsrg_grp_xy_v4_5(
 	enum ipahal_reg_name reg, const void *fields, u32 *val)
 {
-	struct ipahal_reg_rsrc_grp_cfg *grp =
-		(struct ipahal_reg_rsrc_grp_cfg *)fields;
+	struct ipahal_reg_rsrc_grp_xy_cfg *grp =
+		(struct ipahal_reg_rsrc_grp_xy_cfg *)fields;
 
 	IPA_SETFIELD_IN_REG(*val, grp->x_min,
 		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5,
@@ -346,8 +348,8 @@ static void ipareg_construct_rsrg_grp_xy_v4_5(
 static void ipareg_construct_rsrg_grp_xy_v5_0(
 	enum ipahal_reg_name reg, const void *fields, u32 *val)
 {
-	struct ipahal_reg_rsrc_grp_cfg *grp =
-		(struct ipahal_reg_rsrc_grp_cfg *)fields;
+	struct ipahal_reg_rsrc_grp_xy_cfg *grp =
+		(struct ipahal_reg_rsrc_grp_xy_cfg *)fields;
 
 	IPA_SETFIELD_IN_REG(*val, grp->x_min,
 		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5,
@@ -364,6 +366,47 @@ static void ipareg_construct_rsrg_grp_xy_v5_0(
 		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5);
 }
 
+static void ipareg_construct_rsrg_grp_cfg(
+	enum ipahal_reg_name reg, const void *fields, u32 *val)
+{
+	struct ipahal_reg_rsrc_grp_cfg *cfg =
+		(struct ipahal_reg_rsrc_grp_cfg *)fields;
+
+
+	IPA_SETFIELD_IN_REG(*val, cfg->src_grp_index,
+		IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_SHFT,
+		IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_BMSK);
+	IPA_SETFIELD_IN_REG(*val, cfg->src_grp_valid,
+		IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_SHFT,
+		IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_BMSK);
+	IPA_SETFIELD_IN_REG(*val, cfg->dst_pipe_index,
+		IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_SHFT,
+		IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_BMSK);
+	IPA_SETFIELD_IN_REG(*val, cfg->dst_pipe_valid,
+		IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_SHFT,
+		IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_BMSK);
+	IPA_SETFIELD_IN_REG(*val, cfg->dst_grp_index,
+		IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_SHFT,
+		IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_BMSK);
+	IPA_SETFIELD_IN_REG(*val, cfg->dst_grp_valid,
+		IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_SHFT,
+		IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_BMSK);
+}
+
+static void ipareg_construct_rsrg_grp_cfg_ext(
+	enum ipahal_reg_name reg, const void *fields, u32 *val)
+{
+	struct ipahal_reg_rsrc_grp_cfg_ext *cfg =
+		(struct ipahal_reg_rsrc_grp_cfg_ext *)fields;
+
+	IPA_SETFIELD_IN_REG(*val, cfg->index,
+		IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_SHFT,
+		IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_BMSK);
+	IPA_SETFIELD_IN_REG(*val, cfg->valid,
+		IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_SHFT,
+		IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_BMSK);
+}
+
 static void ipareg_construct_hash_cfg_n(
 	enum ipahal_reg_name reg, const void *fields, u32 *val)
 {
@@ -4363,6 +4406,12 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = {
 	[IPA_HW_v5_0][IPA_DST_RSRC_GRP_67_RSRC_TYPE_n] = {
 		ipareg_construct_rsrg_grp_xy_v5_0, ipareg_parse_dummy,
 		0x0000060C, 0x20, 0, 0, 0, 0},
+	[IPA_HW_v5_0][IPA_RSRC_GRP_CFG] = {
+		ipareg_construct_rsrg_grp_cfg, ipareg_parse_dummy,
+		0x000006A0, 0x0, 0, 0, 0, 0},
+	[IPA_HW_v5_0][IPA_RSRC_GRP_CFG_EXT] = {
+		ipareg_construct_rsrg_grp_cfg_ext, ipareg_parse_dummy,
+		0x000006A4, 0x0, 0, 0, 0, 0},
 	[IPA_HW_v5_0][IPA_STAT_QUOTA_BASE_n] = {
 		ipareg_construct_dummy, ipareg_parse_dummy,
 		0x000006D0, 0x4, 0, 0, 0, 0},

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h

@@ -98,6 +98,8 @@ enum ipahal_reg_name {
 	IPA_DST_RSRC_GRP_23_RSRC_TYPE_n,
 	IPA_DST_RSRC_GRP_45_RSRC_TYPE_n,
 	IPA_DST_RSRC_GRP_67_RSRC_TYPE_n,
+	IPA_RSRC_GRP_CFG,
+	IPA_RSRC_GRP_CFG_EXT,
 	IPA_RX_HPS_CLIENTS_MIN_DEPTH_0,
 	IPA_RX_HPS_CLIENTS_MIN_DEPTH_1,
 	IPA_RX_HPS_CLIENTS_MAX_DEPTH_0,
@@ -512,19 +514,48 @@ struct ipahal_reg_debug_cnt_ctrl {
 };
 
 /*
- * struct ipahal_reg_rsrc_grp_cfg - Min/Max values for two rsrc groups
+ * struct ipahal_reg_rsrc_grp_xy_cfg - Min/Max values for two rsrc groups
  * @x_min - first group min value
  * @x_max - first group max value
  * @y_min - second group min value
  * @y_max - second group max value
  */
-struct ipahal_reg_rsrc_grp_cfg {
+struct ipahal_reg_rsrc_grp_xy_cfg {
 	u32 x_min;
 	u32 x_max;
 	u32 y_min;
 	u32 y_max;
 };
 
+/*
+ * struct ipahal_reg_rsrc_grp_cfg - General configuration of resource group behavior
+ * @src_grp_index - Index of special source resource group
+ * @src_grp_valid - Set to 1 if a special source resrouce group exists
+ * @dst_pipe_index - Index of special destination pipe
+ * @dst_pipe_valid - Set to 1 if a special destination pipe exists
+ * @dst_grp_index - Index of special destination resource group
+ * @dst_grp_valid - Set to 1 if a special destination resrouce group exists
+ */
+struct ipahal_reg_rsrc_grp_cfg {
+	u8 src_grp_index;
+	bool src_grp_valid;
+	u8 dst_pipe_index;
+	bool dst_pipe_valid;
+	u8 dst_grp_index;
+	bool dst_grp_valid;
+};
+
+/*
+ * struct ipahal_reg_rsrc_grp_cfg_ext - General configuration of resource group behavior extended
+ * @index - Index of 2nd-priority special source resource group.
+ * 	Will be chosen only in case 1st-level priority group is not requesting service.
+ * @valid - Set to 1 if a 2nd-priority special source resrouce group exists
+ */
+struct ipahal_reg_rsrc_grp_cfg_ext {
+	u8 index;
+	bool valid;
+};
+
 /*
  * struct ipahal_reg_rx_hps_clients - Min or Max values for RX HPS clients
  * @client_minmax - Min or Max values. In case of depth 0 the 4 or 5 values

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h

@@ -804,6 +804,25 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type);
 #define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v5_0 0x1
 #define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v5_0 0
 
+/* IPA_RSRC_GRP_CFG register */
+#define IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_BMSK 0x1
+#define IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_SHFT 0
+#define IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_BMSK 0x70
+#define IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_SHFT 4
+#define IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_BMSK 0x100
+#define IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_SHFT 8
+#define IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_BMSK 0xFF000
+#define IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_SHFT 12
+#define IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_BMSK 0x100000
+#define IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_SHFT 20
+#define IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_BMSK 0x3F000000
+#define IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_SHFT 24
+
+/* IPA_RSRC_GRP_CFG_EXT register */
+#define IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_BMSK 0x0
+#define IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_VALID_SHFT 1
+#define IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_BMSK 0x70
+#define IPA_RSRC_GRP_CFG_EXT_SRC_GRP_2ND_PRIORITY_SPECIAL_INDEX_SHFT 4
 
 /* IPA_ULSO registers */