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@@ -273,9 +273,6 @@ enum {
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WNI_CFG_RPE_AGING_THRESHOLD_FOR_AC3_REG,
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WNI_CFG_NO_OF_ONCHIP_REORDER_SESSIONS,
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WNI_CFG_SINGLE_TID_RC,
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- WNI_CFG_RRM_ENABLED,
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- WNI_CFG_RRM_OPERATING_CHAN_MAX,
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- WNI_CFG_RRM_NON_OPERATING_CHAN_MAX,
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WNI_CFG_TX_PWR_CTRL_ENABLE,
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WNI_CFG_MCAST_BCAST_FILTER_SETTING,
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WNI_CFG_BTC_DHCP_BT_SLOTS_TO_BLOCK,
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@@ -1367,18 +1364,6 @@ enum {
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#define WNI_CFG_SINGLE_TID_RC_STAMAX 1
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#define WNI_CFG_SINGLE_TID_RC_STADEF 1
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-#define WNI_CFG_RRM_ENABLED_STAMIN 0
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-#define WNI_CFG_RRM_ENABLED_STAMAX 1
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-#define WNI_CFG_RRM_ENABLED_STADEF 0
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-
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-#define WNI_CFG_RRM_OPERATING_CHAN_MAX_STAMIN 0
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-#define WNI_CFG_RRM_OPERATING_CHAN_MAX_STAMAX 8
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-#define WNI_CFG_RRM_OPERATING_CHAN_MAX_STADEF 0
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-
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-#define WNI_CFG_RRM_NON_OPERATING_CHAN_MAX_STAMIN 0
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-#define WNI_CFG_RRM_NON_OPERATING_CHAN_MAX_STAMAX 8
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-#define WNI_CFG_RRM_NON_OPERATING_CHAN_MAX_STADEF 0
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-
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#define WNI_CFG_TX_PWR_CTRL_ENABLE_STAMIN 0
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#define WNI_CFG_TX_PWR_CTRL_ENABLE_STAMAX 1
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#define WNI_CFG_TX_PWR_CTRL_ENABLE_STADEF 1
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@@ -1563,8 +1548,8 @@ enum {
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#define WNI_CFG_TDLS_WMM_MODE_ENABLED_STAMAX 1
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#define WNI_CFG_TDLS_WMM_MODE_ENABLED_STADEF 0
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-#define CFG_PARAM_MAX_NUM 289
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-#define CFG_STA_IBUF_MAX_SIZE 237
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+#define CFG_PARAM_MAX_NUM 286
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+#define CFG_STA_IBUF_MAX_SIZE 234
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#define CFG_STA_SBUF_MAX_SIZE 3199
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#define CFG_STA_MAGIC_DWORD 0xbeefbeef
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