qcacmn: HIF changes for QCA5332

1. Changes to support cmem write for AHB devices.
2. Interrupt enablement issue - Incorrect CE address was given which is
fixed.
3. dp_soc_init failure - dev_base_addr of Miami was NULL, which is
fixed.
4. Missing interrupt error logs - Added dummy entires for missing
interrupt in DTS and changes to support shared IRQ in wifi-drivers

Change-Id: I00e7666b2b978c35b5ccec5da21bf442ed0a7998
CRs-Fixed: 3268936
Этот коммит содержится в:
Hariharan Ramanathan
2022-08-10 16:42:12 +05:30
коммит произвёл Madan Koyyalamudi
родитель 19b08fc8ab
Коммит 433a137917
10 изменённых файлов: 74 добавлений и 6 удалений

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@@ -1945,6 +1945,13 @@ void hif_allow_link_low_power_states(struct hif_opaque_softc *hif)
void *hif_get_dev_ba(struct hif_opaque_softc *hif_handle);
void *hif_get_dev_ba_ce(struct hif_opaque_softc *hif_handle);
/**
* hif_get_dev_ba_cmem() - get base address of CMEM
* @hif_ctx - the HIF context
*
*/
void *hif_get_dev_ba_cmem(struct hif_opaque_softc *hif_handle);
/**
* hif_get_soc_version() - get soc major version from target info
* @hif_ctx - the HIF context

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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -587,6 +588,8 @@ struct host_shadow_regs_s {
*
* @d_CE_DEBUG_SEL_MASK: Bits indicating Copy Engine FSM Debug Status
*
* @d_HOST_CMEM_ADDRESS: Base address of CMEM
*
*/
struct ce_reg_def {
/* copy_engine.c */
@@ -661,6 +664,7 @@ struct ce_reg_def {
uint32_t d_HOST_IE_REG2_CE_LSB;
uint32_t d_HOST_IE_REG3_CE_LSB;
uint32_t d_HOST_CE_ADDRESS;
uint32_t d_HOST_CMEM_ADDRESS;
};
#endif

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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
* tCopyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -378,6 +379,10 @@ struct targetdef_s *MY_TARGET_DEF = &my_target_def;
#if !defined(HOST_CE_ADDRESS)
#define HOST_CE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
#endif
#if !defined(HOST_CMEM_ADDRESS)
#define HOST_CMEM_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
#endif
static struct ce_reg_def my_ce_reg_def = {
/* copy_engine.c */
@@ -464,7 +469,8 @@ static struct ce_reg_def my_ce_reg_def = {
= A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES,
.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS
= A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS,
.d_HOST_CE_ADDRESS = HOST_CE_ADDRESS
.d_HOST_CE_ADDRESS = HOST_CE_ADDRESS,
.d_HOST_CMEM_ADDRESS = HOST_CMEM_ADDRESS
};
struct ce_reg_def *MY_CEREG_DEF = &my_ce_reg_def;

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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -211,6 +212,7 @@
#define HOST_IE_REG3_CE_LSB (scn->target_ce_def->d_HOST_IE_REG3_CE_LSB)
#define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS)
#define HOST_CE_ADDRESS (scn->target_ce_def->d_HOST_CE_ADDRESS)
#define HOST_CMEM_ADDRESS (scn->target_ce_def->d_HOST_CMEM_ADDRESS)
#define SRC_WATERMARK_LOW_SET(x) \
(((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)

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@@ -494,6 +494,21 @@ uint32_t hif_get_soc_version(struct hif_opaque_softc *hif_handle)
qdf_export_symbol(hif_get_soc_version);
/**
* hif_get_dev_ba_cmem(): API to get device ce base address.
* @scn: scn
*
* Return: dev mem base address for CMEM
*/
void *hif_get_dev_ba_cmem(struct hif_opaque_softc *hif_handle)
{
struct hif_softc *scn = (struct hif_softc *)hif_handle;
return scn->mem_cmem;
}
qdf_export_symbol(hif_get_dev_ba_cmem);
#ifdef FEATURE_RUNTIME_PM
void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get)
{

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@@ -249,6 +249,7 @@ struct hif_softc {
struct hif_target_info target_info;
void __iomem *mem;
void __iomem *mem_ce;
void __iomem *mem_cmem;
enum qdf_bus_type bus_type;
struct hif_bus_ops bus_ops;
void *ce_id_to_state[CE_COUNT_MAX];

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@@ -119,6 +119,7 @@ struct hif_pci_softc {
struct HIF_CE_state ce_sc;
void __iomem *mem; /* PCI address. */
void __iomem *mem_ce; /* PCI address for CE. */
void __iomem *mem_cmem; /* PCI address for CMEM. */
size_t mem_len;
struct device *dev; /* For efficiency, should be first in struct */

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@@ -153,17 +153,19 @@
#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
#define HOST_CMEM_ADDRESS 0xC100000
#define HOST_CE_ADDRESS CE_CFG_WFSS_CE_REG_BASE
#define HOST_IE_ADDRESS \
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
WFSS_CE_COMMON_REG_REG_BASE)
WFSS_CE_COMMON_REG_REG_BASE_OFFS)
#define HOST_IE_REG1_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT
#define HOST_IE_ADDRESS_2 \
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(\
WFSS_CE_COMMON_REG_REG_BASE)
WFSS_CE_COMMON_REG_REG_BASE_OFFS)
#define HOST_IE_REG2_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT
#define HOST_IE_ADDRESS_3 \
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
WFSS_CE_COMMON_REG_REG_BASE)
WFSS_CE_COMMON_REG_REG_BASE_OFFS)
#define HOST_IE_REG3_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT
#define HOST_IE_COPY_COMPLETE_MASK MISSING

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@@ -207,11 +207,15 @@ static void hif_ahb_get_soc_info_pld(struct hif_pci_softc *sc,
{
struct pld_soc_info info;
int ret = 0;
struct hif_softc *scn = HIF_GET_SOFTC(sc);
ret = pld_get_soc_info(dev, &info);
sc->mem = info.v_addr;
sc->ce_sc.ol_sc.mem = info.v_addr;
sc->ce_sc.ol_sc.mem_pa = info.p_addr;
/* dev_mem_info[0] is for CMEM */
scn->cmem_start = info.dev_mem_info[0].start;
scn->cmem_size = info.dev_mem_info[0].size;
}
int hif_ahb_configure_irq_by_ceid(struct hif_softc *scn, int ce_id)
@@ -313,7 +317,7 @@ int hif_ahb_configure_grp_irq(struct hif_softc *scn,
ret = pfrm_request_irq(scn->qdf_dev->dev,
irq, hif_ext_group_interrupt_handler,
IRQF_TRIGGER_RISING,
IRQF_TRIGGER_RISING | IRQF_SHARED,
ic_irqname[hif_ext_group->irq[j]],
hif_ext_group);
if (ret) {
@@ -412,6 +416,10 @@ void hif_ahb_disable_bus(struct hif_softc *scn)
sc->mem_ce = NULL;
scn->mem_ce = NULL;
}
if (sc->mem_cmem) {
iounmap(sc->mem_cmem);
sc->mem_cmem = NULL;
}
mem = (void __iomem *)sc->mem;
if (mem) {
pfrm_devm_iounmap(&pdev->dev, mem);
@@ -466,8 +474,12 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
return QDF_STATUS_E_FAILURE;
}
if (target_type == TARGET_TYPE_QCN6122) {
if (target_type == TARGET_TYPE_QCN6122 ||
target_type == TARGET_TYPE_QCA5332) {
hif_ahb_get_soc_info_pld(sc, dev);
}
if (target_type == TARGET_TYPE_QCN6122) {
hif_update_irq_ops_with_pci(ol_sc);
} else {
status = pfrm_platform_get_resource(&pdev->dev,
@@ -546,6 +558,22 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
ol_sc->mem_ce = sc->mem_ce;
}
/*
* In QCA5332 CMEM region is outside WCSS block.
* Allocate separate I/O remap to access CMEM address.
*/
if (tgt_info->target_type == TARGET_TYPE_QCA5332) {
struct hif_softc *scn = HIF_GET_SOFTC(sc);
sc->mem_cmem = ioremap_nocache(HOST_CMEM_ADDRESS,
HOST_CMEM_SIZE);
if (IS_ERR(sc->mem_cmem)) {
hif_err("CE: ioremap failed");
return QDF_STATUS_E_IO;
}
ol_sc->mem_cmem = sc->mem_cmem;
}
hif_info("X - hif_type = 0x%x, target_type = 0x%x",
hif_type, target_type);

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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -45,6 +46,7 @@
#define TCSR_WCSS0_HALTACK 0x52010
#define TCSR_WCSS1_HALTACK 0x52014
#define ATH_AHB_RESET_WAIT_MAX 10 /* Ms */
#define HOST_CMEM_SIZE 0x40000
#define HOST_CE_SIZE 0x200000
irqreturn_t hif_ahb_interrupt_handler(int irq, void *context);