qcacmn: HIF changes for QCA5332
1. Changes to support cmem write for AHB devices. 2. Interrupt enablement issue - Incorrect CE address was given which is fixed. 3. dp_soc_init failure - dev_base_addr of Miami was NULL, which is fixed. 4. Missing interrupt error logs - Added dummy entires for missing interrupt in DTS and changes to support shared IRQ in wifi-drivers Change-Id: I00e7666b2b978c35b5ccec5da21bf442ed0a7998 CRs-Fixed: 3268936
Этот коммит содержится в:

коммит произвёл
Madan Koyyalamudi

родитель
19b08fc8ab
Коммит
433a137917
@@ -1945,6 +1945,13 @@ void hif_allow_link_low_power_states(struct hif_opaque_softc *hif)
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void *hif_get_dev_ba(struct hif_opaque_softc *hif_handle);
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void *hif_get_dev_ba_ce(struct hif_opaque_softc *hif_handle);
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/**
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* hif_get_dev_ba_cmem() - get base address of CMEM
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* @hif_ctx - the HIF context
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*
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*/
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void *hif_get_dev_ba_cmem(struct hif_opaque_softc *hif_handle);
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/**
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* hif_get_soc_version() - get soc major version from target info
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* @hif_ctx - the HIF context
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@@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2015-2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@@ -587,6 +588,8 @@ struct host_shadow_regs_s {
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*
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* @d_CE_DEBUG_SEL_MASK: Bits indicating Copy Engine FSM Debug Status
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*
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* @d_HOST_CMEM_ADDRESS: Base address of CMEM
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*
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*/
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struct ce_reg_def {
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/* copy_engine.c */
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@@ -661,6 +664,7 @@ struct ce_reg_def {
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uint32_t d_HOST_IE_REG2_CE_LSB;
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uint32_t d_HOST_IE_REG3_CE_LSB;
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uint32_t d_HOST_CE_ADDRESS;
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uint32_t d_HOST_CMEM_ADDRESS;
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};
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#endif
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@@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
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* tCopyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@@ -378,6 +379,10 @@ struct targetdef_s *MY_TARGET_DEF = &my_target_def;
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#if !defined(HOST_CE_ADDRESS)
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#define HOST_CE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
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#endif
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#if !defined(HOST_CMEM_ADDRESS)
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#define HOST_CMEM_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
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#endif
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static struct ce_reg_def my_ce_reg_def = {
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/* copy_engine.c */
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@@ -464,7 +469,8 @@ static struct ce_reg_def my_ce_reg_def = {
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= A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES,
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.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS
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= A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS,
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.d_HOST_CE_ADDRESS = HOST_CE_ADDRESS
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.d_HOST_CE_ADDRESS = HOST_CE_ADDRESS,
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.d_HOST_CMEM_ADDRESS = HOST_CMEM_ADDRESS
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};
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struct ce_reg_def *MY_CEREG_DEF = &my_ce_reg_def;
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@@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2015-2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@@ -211,6 +212,7 @@
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#define HOST_IE_REG3_CE_LSB (scn->target_ce_def->d_HOST_IE_REG3_CE_LSB)
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#define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS)
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#define HOST_CE_ADDRESS (scn->target_ce_def->d_HOST_CE_ADDRESS)
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#define HOST_CMEM_ADDRESS (scn->target_ce_def->d_HOST_CMEM_ADDRESS)
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#define SRC_WATERMARK_LOW_SET(x) \
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(((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
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@@ -494,6 +494,21 @@ uint32_t hif_get_soc_version(struct hif_opaque_softc *hif_handle)
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qdf_export_symbol(hif_get_soc_version);
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/**
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* hif_get_dev_ba_cmem(): API to get device ce base address.
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* @scn: scn
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*
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* Return: dev mem base address for CMEM
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*/
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void *hif_get_dev_ba_cmem(struct hif_opaque_softc *hif_handle)
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{
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struct hif_softc *scn = (struct hif_softc *)hif_handle;
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return scn->mem_cmem;
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}
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qdf_export_symbol(hif_get_dev_ba_cmem);
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#ifdef FEATURE_RUNTIME_PM
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void hif_runtime_prevent_linkdown(struct hif_softc *scn, bool is_get)
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{
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@@ -249,6 +249,7 @@ struct hif_softc {
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struct hif_target_info target_info;
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void __iomem *mem;
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void __iomem *mem_ce;
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void __iomem *mem_cmem;
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enum qdf_bus_type bus_type;
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struct hif_bus_ops bus_ops;
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void *ce_id_to_state[CE_COUNT_MAX];
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@@ -119,6 +119,7 @@ struct hif_pci_softc {
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struct HIF_CE_state ce_sc;
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void __iomem *mem; /* PCI address. */
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void __iomem *mem_ce; /* PCI address for CE. */
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void __iomem *mem_cmem; /* PCI address for CMEM. */
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size_t mem_len;
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struct device *dev; /* For efficiency, should be first in struct */
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@@ -153,17 +153,19 @@
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#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
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#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
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#define HOST_CMEM_ADDRESS 0xC100000
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#define HOST_CE_ADDRESS CE_CFG_WFSS_CE_REG_BASE
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#define HOST_IE_ADDRESS \
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HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
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WFSS_CE_COMMON_REG_REG_BASE)
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WFSS_CE_COMMON_REG_REG_BASE_OFFS)
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#define HOST_IE_REG1_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT
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#define HOST_IE_ADDRESS_2 \
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HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(\
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WFSS_CE_COMMON_REG_REG_BASE)
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WFSS_CE_COMMON_REG_REG_BASE_OFFS)
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#define HOST_IE_REG2_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT
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#define HOST_IE_ADDRESS_3 \
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HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
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WFSS_CE_COMMON_REG_REG_BASE)
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WFSS_CE_COMMON_REG_REG_BASE_OFFS)
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#define HOST_IE_REG3_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT
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#define HOST_IE_COPY_COMPLETE_MASK MISSING
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@@ -207,11 +207,15 @@ static void hif_ahb_get_soc_info_pld(struct hif_pci_softc *sc,
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{
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struct pld_soc_info info;
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int ret = 0;
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struct hif_softc *scn = HIF_GET_SOFTC(sc);
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ret = pld_get_soc_info(dev, &info);
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sc->mem = info.v_addr;
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sc->ce_sc.ol_sc.mem = info.v_addr;
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sc->ce_sc.ol_sc.mem_pa = info.p_addr;
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/* dev_mem_info[0] is for CMEM */
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scn->cmem_start = info.dev_mem_info[0].start;
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scn->cmem_size = info.dev_mem_info[0].size;
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}
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int hif_ahb_configure_irq_by_ceid(struct hif_softc *scn, int ce_id)
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@@ -313,7 +317,7 @@ int hif_ahb_configure_grp_irq(struct hif_softc *scn,
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ret = pfrm_request_irq(scn->qdf_dev->dev,
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irq, hif_ext_group_interrupt_handler,
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IRQF_TRIGGER_RISING,
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IRQF_TRIGGER_RISING | IRQF_SHARED,
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ic_irqname[hif_ext_group->irq[j]],
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hif_ext_group);
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if (ret) {
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@@ -412,6 +416,10 @@ void hif_ahb_disable_bus(struct hif_softc *scn)
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sc->mem_ce = NULL;
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scn->mem_ce = NULL;
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}
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if (sc->mem_cmem) {
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iounmap(sc->mem_cmem);
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sc->mem_cmem = NULL;
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}
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mem = (void __iomem *)sc->mem;
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if (mem) {
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pfrm_devm_iounmap(&pdev->dev, mem);
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@@ -466,8 +474,12 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
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return QDF_STATUS_E_FAILURE;
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}
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if (target_type == TARGET_TYPE_QCN6122) {
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if (target_type == TARGET_TYPE_QCN6122 ||
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target_type == TARGET_TYPE_QCA5332) {
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hif_ahb_get_soc_info_pld(sc, dev);
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}
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if (target_type == TARGET_TYPE_QCN6122) {
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hif_update_irq_ops_with_pci(ol_sc);
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} else {
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status = pfrm_platform_get_resource(&pdev->dev,
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@@ -546,6 +558,22 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
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ol_sc->mem_ce = sc->mem_ce;
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}
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/*
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* In QCA5332 CMEM region is outside WCSS block.
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* Allocate separate I/O remap to access CMEM address.
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*/
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if (tgt_info->target_type == TARGET_TYPE_QCA5332) {
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struct hif_softc *scn = HIF_GET_SOFTC(sc);
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sc->mem_cmem = ioremap_nocache(HOST_CMEM_ADDRESS,
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HOST_CMEM_SIZE);
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if (IS_ERR(sc->mem_cmem)) {
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hif_err("CE: ioremap failed");
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return QDF_STATUS_E_IO;
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}
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ol_sc->mem_cmem = sc->mem_cmem;
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}
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hif_info("X - hif_type = 0x%x, target_type = 0x%x",
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hif_type, target_type);
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@@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@@ -45,6 +46,7 @@
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#define TCSR_WCSS0_HALTACK 0x52010
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#define TCSR_WCSS1_HALTACK 0x52014
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#define ATH_AHB_RESET_WAIT_MAX 10 /* Ms */
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#define HOST_CMEM_SIZE 0x40000
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#define HOST_CE_SIZE 0x200000
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irqreturn_t hif_ahb_interrupt_handler(int irq, void *context);
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