Merge "msm: camera: csiphy: Add support for CPHY dynamic lane configuration" into camera-kernel.lnx.4.0

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -145,75 +145,105 @@ static int32_t cam_csiphy_update_secure_info(
 }
 
 static int cam_csiphy_get_lane_enable(
-	struct csiphy_device *csiphy, int index, uint32_t *lane_enable)
+	struct csiphy_device *csiphy, int index,
+	uint16_t lane_assign, uint32_t *lane_enable)
 {
 	uint32_t lane_select = 0;
-	uint16_t lane_assign = csiphy->csiphy_info[index].lane_assign;
-	uint8_t lane_cnt = csiphy->csiphy_info[index].lane_cnt;
-	int rc = 0;
 
-	while (lane_cnt--) {
-		if (csiphy->csiphy_info[index].csiphy_3phase) {
-			switch (lane_assign & 0xF) {
-			case 0x0:
-				lane_select |= CPHY_LANE_0;
-				break;
-			case 0x1:
-				lane_select |= CPHY_LANE_1;
-				break;
-			case 0x2:
-				lane_select |= CPHY_LANE_2;
-				break;
-			default:
-				CAM_ERR(CAM_CSIPHY,
-					"Wrong lane configuration for CPHY : %d",
-					lane_assign);
-				*lane_enable = 0;
-				return -EINVAL;
-			}
-		} else {
-			switch (lane_assign & 0xF) {
-			case 0x0:
-				lane_select |= DPHY_LANE_0;
-				lane_select |= DPHY_CLK_LN;
-				break;
-			case 0x1:
-				lane_select |= DPHY_LANE_1;
-				lane_select |= DPHY_CLK_LN;
-				break;
-			case 0x2:
-				lane_select |= DPHY_LANE_2;
-				if (csiphy->combo_mode)
-					lane_select |= DPHY_LANE_3;
-				else
-					lane_select |= DPHY_CLK_LN;
-				break;
-			case 0x3:
-				if (csiphy->combo_mode) {
-					CAM_ERR(CAM_CSIPHY,
-						"Wrong lane configuration for DPHYCombo: %d",
-						lane_assign);
-					*lane_enable = 0;
-					return -EINVAL;
-				}
+	if (csiphy->csiphy_info[index].csiphy_3phase) {
+		switch (lane_assign & 0xF) {
+		case 0x0:
+			lane_select |= CPHY_LANE_0;
+			break;
+		case 0x1:
+			lane_select |= CPHY_LANE_1;
+			break;
+		case 0x2:
+			lane_select |= CPHY_LANE_2;
+			break;
+		default:
+			CAM_ERR(CAM_CSIPHY,
+				"Wrong lane configuration for CPHY : %d",
+				lane_assign);
+			*lane_enable = 0;
+			return -EINVAL;
+		}
+	} else {
+		switch (lane_assign & 0xF) {
+		case 0x0:
+			lane_select |= DPHY_LANE_0;
+			lane_select |= DPHY_CLK_LN;
+			break;
+		case 0x1:
+			lane_select |= DPHY_LANE_1;
+			lane_select |= DPHY_CLK_LN;
+			break;
+		case 0x2:
+			lane_select |= DPHY_LANE_2;
+			if (csiphy->combo_mode)
 				lane_select |= DPHY_LANE_3;
+			else
 				lane_select |= DPHY_CLK_LN;
-				break;
-			default:
+			break;
+		case 0x3:
+			if (csiphy->combo_mode) {
 				CAM_ERR(CAM_CSIPHY,
-					"Wrong lane configuration for DPHY: %d",
+					"Wrong lane configuration for DPHYCombo: %d",
 					lane_assign);
 				*lane_enable = 0;
 				return -EINVAL;
 			}
+			lane_select |= DPHY_LANE_3;
+			lane_select |= DPHY_CLK_LN;
+			break;
+		default:
+			CAM_ERR(CAM_CSIPHY,
+				"Wrong lane configuration for DPHY: %d",
+				lane_assign);
+			*lane_enable = 0;
+			return -EINVAL;
 		}
-		lane_assign >>= 4;
 	}
 
 	CAM_DBG(CAM_CSIPHY, "Lane_enable: 0x%x", lane_enable);
 	*lane_enable = lane_select;
 
-	return rc;
+	return 0;
+}
+
+static int cam_csiphy_sanitize_lane_cnt(
+	struct csiphy_device *csiphy_dev,
+	int32_t index, uint8_t lane_cnt)
+{
+	uint8_t max_supported_lanes = 0;
+
+	if (csiphy_dev->combo_mode) {
+		if (csiphy_dev->csiphy_info[index].csiphy_3phase)
+			max_supported_lanes = 1;
+		else
+			max_supported_lanes = 2;
+	} else if (csiphy_dev->cphy_dphy_combo_mode) {
+		/* 2DPHY + 1CPHY or 2CPHY + 1DPHY */
+		if (csiphy_dev->csiphy_info[index].csiphy_3phase)
+			max_supported_lanes = 2;
+		else
+			max_supported_lanes = 2;
+	} else {
+		/* Mission Mode */
+		if (csiphy_dev->csiphy_info[index].csiphy_3phase)
+			max_supported_lanes = 3;
+		else
+			max_supported_lanes = 4;
+	}
+
+	if (lane_cnt <= 0 || lane_cnt > max_supported_lanes) {
+		CAM_ERR(CAM_CSIPHY,
+			"wrong lane_cnt configuration: expected max lane_cnt: %u received lane_cnt: %u",
+			max_supported_lanes, lane_cnt);
+		return -EINVAL;
+	}
+
+	return 0;
 }
 
 int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
@@ -230,6 +260,8 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 	size_t                  remain_len;
 	int                     index;
 	uint32_t                lane_enable = 0;
+	uint16_t                lane_assign = 0;
+	uint8_t                 lane_cnt = 0;
 
 	if (!cfg_dev || !csiphy_dev) {
 		CAM_ERR(CAM_CSIPHY, "Invalid Args");
@@ -294,6 +326,15 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 		return -EINVAL;
 	}
 
+	rc = cam_csiphy_sanitize_lane_cnt(csiphy_dev, index,
+		cam_cmd_csiphy_info->lane_cnt);
+	if (rc) {
+		CAM_ERR(CAM_CSIPHY,
+			"Wrong configuration lane_cnt: %u",
+			cam_cmd_csiphy_info->lane_cnt);
+		return rc;
+	}
+
 	csiphy_dev->csiphy_info[index].lane_cnt = cam_cmd_csiphy_info->lane_cnt;
 	csiphy_dev->csiphy_info[index].lane_assign =
 		cam_cmd_csiphy_info->lane_assign;
@@ -305,23 +346,29 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 	csiphy_dev->csiphy_info[index].secure_mode =
 		cam_cmd_csiphy_info->secure_mode;
 
-	rc = cam_csiphy_get_lane_enable(csiphy_dev, index, &lane_enable);
-	if (rc) {
-		CAM_ERR(CAM_CSIPHY, "Wrong lane configuration: %d",
-			csiphy_dev->csiphy_info[index].lane_assign);
-		if ((csiphy_dev->combo_mode) ||
-			(csiphy_dev->cphy_dphy_combo_mode)) {
-			CAM_DBG(CAM_CSIPHY,
-				"Resetting error to zero for other devices to configure");
-			rc = 0;
+	lane_assign = csiphy_dev->csiphy_info[index].lane_assign;
+	lane_cnt = csiphy_dev->csiphy_info[index].lane_cnt;
+
+	while (lane_cnt--) {
+		rc = cam_csiphy_get_lane_enable(csiphy_dev, index,
+			(lane_assign & 0xF), &lane_enable);
+		if (rc) {
+			CAM_ERR(CAM_CSIPHY, "Wrong lane configuration: %d",
+				csiphy_dev->csiphy_info[index].lane_assign);
+			if ((csiphy_dev->combo_mode) ||
+				(csiphy_dev->cphy_dphy_combo_mode)) {
+				CAM_DBG(CAM_CSIPHY,
+					"Resetting error to zero for other devices to configure");
+				rc = 0;
+			}
+			lane_enable = 0;
+			csiphy_dev->csiphy_info[index].lane_enable = lane_enable;
+			goto reset_settings;
 		}
-		lane_enable = 0;
-		csiphy_dev->csiphy_info[index].lane_enable = lane_enable;
-		goto reset_settings;
+		csiphy_dev->csiphy_info[index].lane_enable |= lane_enable;
+		lane_assign >>= 4;
 	}
 
-	csiphy_dev->csiphy_info[index].lane_enable = lane_enable;
-
 	if (cam_cmd_csiphy_info->secure_mode == 1)
 		cam_csiphy_update_secure_info(csiphy_dev,
 			index);
@@ -372,66 +419,6 @@ void cam_csiphy_cphy_irq_config(struct csiphy_device *csiphy_dev)
 			csiphy_dev->ctrl_reg->csiphy_irq_reg[i].reg_addr);
 }
 
-static void cam_csiphy_cphy_data_rate_config(
-	struct csiphy_device *csiphy_device, int32_t idx)
-{
-	int i = 0, j = 0;
-	uint64_t phy_data_rate = 0;
-	void __iomem *csiphybase = NULL;
-	ssize_t num_table_entries = 0;
-	struct data_rate_settings_t *settings_table = NULL;
-
-	if ((csiphy_device == NULL) ||
-		(csiphy_device->ctrl_reg == NULL) ||
-		(csiphy_device->ctrl_reg->data_rates_settings_table == NULL)) {
-		CAM_DBG(CAM_CSIPHY,
-			"Data rate specific register table not found");
-		return;
-	}
-
-	phy_data_rate = csiphy_device->csiphy_info[idx].data_rate;
-	csiphybase =
-		csiphy_device->soc_info.reg_map[0].mem_base;
-	settings_table =
-		csiphy_device->ctrl_reg->data_rates_settings_table;
-	num_table_entries =
-		settings_table->num_data_rate_settings;
-
-	CAM_DBG(CAM_CSIPHY, "required data rate : %llu", phy_data_rate);
-	for (i = 0; i < num_table_entries; i++) {
-		struct data_rate_reg_info_t *drate_settings =
-			settings_table->data_rate_settings;
-		uint64_t bandwidth =
-			drate_settings[i].bandwidth;
-		ssize_t  num_reg_entries =
-		drate_settings[i].data_rate_reg_array_size;
-
-		if (phy_data_rate > bandwidth) {
-			CAM_DBG(CAM_CSIPHY,
-				"Skipping table [%d] %llu required: %llu",
-				i, bandwidth, phy_data_rate);
-			continue;
-		}
-
-		CAM_DBG(CAM_CSIPHY,
-			"table[%d] BW : %llu Selected", i, bandwidth);
-		for (j = 0; j < num_reg_entries; j++) {
-			uint32_t reg_addr =
-			drate_settings[i].csiphy_data_rate_regs[j].reg_addr;
-
-			uint32_t reg_data =
-			drate_settings[i].csiphy_data_rate_regs[j].reg_data;
-
-			CAM_DBG(CAM_CSIPHY,
-				"writing reg : %x val : %x",
-						reg_addr, reg_data);
-			cam_io_w_mb(reg_data,
-				csiphybase + reg_addr);
-		}
-		break;
-	}
-}
-
 void cam_csiphy_cphy_irq_disable(struct csiphy_device *csiphy_dev)
 {
 	int32_t i;
@@ -482,6 +469,122 @@ irqreturn_t cam_csiphy_irq(int irq_num, void *data)
 	return IRQ_HANDLED;
 }
 
+static int cam_csiphy_cphy_get_data_rate_lane_idx(
+	struct csiphy_device *csiphy_dev, int32_t index,
+	uint16_t lane_assign,
+	struct data_rate_reg_info_t *drate_settings)
+{
+	int rc = 0;
+	int idx = -1;
+	uint32_t lane_enable;
+
+	rc = cam_csiphy_get_lane_enable(csiphy_dev, index,
+		lane_assign, &lane_enable);
+	if (rc) {
+		CAM_ERR(CAM_CSIPHY,
+			"Wrong configuration for lane_assign: %u", lane_assign);
+		return rc;
+	}
+
+	for (idx =  0; idx < CAM_CSIPHY_MAX_CPHY_LANES; idx++) {
+		if (lane_enable & drate_settings->per_lane_info[idx].lane_identifier)
+			return idx;
+	}
+
+	if (idx == CAM_CSIPHY_MAX_CPHY_LANES) {
+		CAM_ERR(CAM_CSIPHY,
+			"Lane not found in datarate table");
+		rc = -EINVAL;
+	}
+
+	return rc;
+}
+
+static int cam_csiphy_cphy_data_rate_config(
+	struct csiphy_device *csiphy_device, int32_t idx)
+{
+	int i = 0;
+	int lane_idx = -1;
+	int data_rate_idx = -1;
+	uint64_t phy_data_rate = 0;
+	void __iomem *csiphybase = NULL;
+	ssize_t num_table_entries = 0;
+	struct data_rate_settings_t *settings_table = NULL;
+	struct csiphy_cphy_per_lane_info *per_lane = NULL;
+	uint32_t lane_enable = 0;
+	uint8_t lane_cnt = 0;
+	uint16_t lane_assign = 0;
+
+	if ((csiphy_device == NULL) ||
+		(csiphy_device->ctrl_reg == NULL) ||
+		(csiphy_device->ctrl_reg->data_rates_settings_table == NULL)) {
+		CAM_DBG(CAM_CSIPHY,
+			"Data rate specific register table not found");
+		return -EINVAL;
+	}
+
+	phy_data_rate = csiphy_device->csiphy_info[idx].data_rate;
+	csiphybase =
+		csiphy_device->soc_info.reg_map[0].mem_base;
+	settings_table =
+		csiphy_device->ctrl_reg->data_rates_settings_table;
+	num_table_entries =
+		settings_table->num_data_rate_settings;
+	lane_cnt = csiphy_device->csiphy_info[idx].lane_cnt;
+
+	CAM_DBG(CAM_CSIPHY, "required data rate : %llu", phy_data_rate);
+	for (data_rate_idx = 0; data_rate_idx < num_table_entries;
+			data_rate_idx++) {
+		struct data_rate_reg_info_t *drate_settings =
+			settings_table->data_rate_settings;
+		uint64_t bandwidth = drate_settings[data_rate_idx].bandwidth;
+		ssize_t  num_reg_entries =
+			drate_settings[data_rate_idx].data_rate_reg_array_size;
+		if (phy_data_rate > bandwidth) {
+			CAM_DBG(CAM_CSIPHY,
+				"Skipping table [%d] with BW: %llu, Required data_rate: %llu",
+				data_rate_idx, bandwidth, phy_data_rate);
+			continue;
+		}
+
+		CAM_DBG(CAM_CSIPHY, "table[%d] BW : %llu Selected",
+			data_rate_idx, bandwidth);
+		lane_enable = csiphy_device->csiphy_info[idx].lane_enable;
+		lane_assign = csiphy_device->csiphy_info[idx].lane_assign;
+		lane_idx = -1;
+
+		while (lane_cnt--) {
+			lane_idx = cam_csiphy_cphy_get_data_rate_lane_idx(
+				csiphy_device, idx, (lane_assign & 0xF),
+				&drate_settings[data_rate_idx]);
+			if (lane_idx < 0) {
+				CAM_ERR(CAM_CSIPHY,
+					"Lane_assign %u failed to find the lane for datarate_idx: %d",
+					lane_assign, data_rate_idx);
+				return -EINVAL;
+			}
+
+			lane_assign >>= 4;
+			per_lane = &drate_settings[data_rate_idx].per_lane_info[lane_idx];
+
+			for (i = 0; i < num_reg_entries; i++) {
+				uint32_t reg_addr =
+				per_lane->csiphy_data_rate_regs[i].reg_addr;
+
+				uint32_t reg_data =
+				per_lane->csiphy_data_rate_regs[i].reg_data;
+
+				CAM_DBG(CAM_CSIPHY, "writing reg : %x val : %x",
+					reg_addr, reg_data);
+				cam_io_w_mb(reg_data, csiphybase + reg_addr);
+			}
+		}
+		break;
+	}
+
+	return 0;
+}
+
 int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
 	int32_t dev_handle)
 {
@@ -668,8 +771,15 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
 		}
 	}
 
-	if (csiphy_dev->csiphy_info[index].csiphy_3phase)
-		cam_csiphy_cphy_data_rate_config(csiphy_dev, index);
+	if (csiphy_dev->csiphy_info[index].csiphy_3phase) {
+		rc = cam_csiphy_cphy_data_rate_config(csiphy_dev, index);
+		if (rc) {
+			CAM_ERR(CAM_CSIPHY,
+				"Date rate specific configuration failed rc: %d",
+				rc);
+			return rc;
+		}
+	}
 
 	cam_csiphy_cphy_irq_config(csiphy_dev);
 
@@ -1175,9 +1285,8 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 			if (csiphy_dev->csiphy_info[offset].secure_mode == 1) {
 				if (cam_cpas_is_feature_supported(
 					CAM_CPAS_SECURE_CAMERA_ENABLE) != 1) {
-					CAM_WARN(CAM_CSIPHY,
+					CAM_ERR(CAM_CSIPHY,
 						"sec_cam: camera fuse bit not set");
-					rc = 0;
 					goto release_mutex;
 				}
 
@@ -1187,23 +1296,30 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 					csiphy_dev->csiphy_info[offset]
 						.secure_mode =
 						CAM_SECURE_MODE_NON_SECURE;
-					CAM_WARN(CAM_CSIPHY,
+					CAM_ERR(CAM_CSIPHY,
 						"sec_cam: notify failed: rc: %d",
 						rc);
-					rc = 0;
 					goto release_mutex;
 				}
 			}
-			if (csiphy_dev->csiphy_info[offset].csiphy_3phase)
-				cam_csiphy_cphy_data_rate_config(
+
+			if (csiphy_dev->csiphy_info[offset].csiphy_3phase) {
+				rc = cam_csiphy_cphy_data_rate_config(
 					csiphy_dev, offset);
+				if (rc) {
+					CAM_ERR(CAM_CSIPHY,
+						"Data rate specific configuration failed rc: %d",
+						rc);
+					goto release_mutex;
+				}
+			}
 
 			rc = cam_csiphy_update_lane(csiphy_dev, offset, true);
 			if (csiphy_dump == 1)
 				cam_csiphy_mem_dmp(&csiphy_dev->soc_info);
 			if (rc) {
-				CAM_WARN(CAM_CSIPHY,
-					"csiphy_config_dev failed");
+				CAM_ERR(CAM_CSIPHY,
+					"Update enable lane failed, rc: %d", rc);
 				goto release_mutex;
 			}
 
@@ -1236,7 +1352,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 				CAM_ERR(CAM_CSIPHY,
 					"sec_cam: camera fuse bit not set");
 				cam_cpas_stop(csiphy_dev->cpas_handle);
-				rc = -1;
+				rc = -EINVAL;
 				goto release_mutex;
 			}
 

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

@@ -152,6 +152,11 @@ struct csiphy_reg_t {
 
 struct csiphy_device;
 
+struct csiphy_cphy_per_lane_info {
+	uint8_t lane_identifier;
+	struct csiphy_reg_t csiphy_data_rate_regs[MAX_DATA_RATE_REGS];
+};
+
 /*
  * struct data_rate_reg_info_t
  * @bandwidth: max bandwidth supported by this reg settings
@@ -161,7 +166,8 @@ struct csiphy_device;
 struct data_rate_reg_info_t {
 	uint64_t bandwidth;
 	ssize_t  data_rate_reg_array_size;
-	struct csiphy_reg_t csiphy_data_rate_regs[MAX_DATA_RATE_REGS];
+	struct   csiphy_cphy_per_lane_info per_lane_info[
+			CAM_CSIPHY_MAX_CPHY_LANES];
 };
 
 /**

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h

@@ -396,58 +396,135 @@ struct data_rate_settings_t data_rate_delta_table_1_2_1 = {
 		{
 			/* (2.5 * 10**3 * 2.28) rounded value*/
 			.bandwidth = 5700000000,
-			.data_rate_reg_array_size = 9,
-			.csiphy_data_rate_regs = {
-				{0x144, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x344, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x544, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x164, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x364, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x564, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
-			}
+			.data_rate_reg_array_size = 3,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x144, 0x32, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x164, 0x0B, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x16C, 0x25, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x344, 0x32, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x364, 0x0B, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x36C, 0x25, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x544, 0x32, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x564, 0x0B, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x56C, 0x25, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
 		},
 		{
 			/* (3.5 * 10**3 * 2.28) rounded value */
 			.bandwidth = 7980000000,
-			.data_rate_reg_array_size = 12,
-			.csiphy_data_rate_regs = {
-				{0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x16C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x36C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x56C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xBB4, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS},
+			.data_rate_reg_array_size = 4,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x144, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x164, 0x33, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x16C, 0x1D, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x9B4, 0x03, 0x01,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x344, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x364, 0x33, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x36C, 0x1D, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xAB4, 0x03, 0x01,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x544, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x564, 0x33, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x56C, 0x1D, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xBB4, 0x03, 0x01,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
 			},
 		},
 		{
 			/* (4.5 * 10**3 * 2.28) rounded value */
 			.bandwidth = 10260000000,
-			.data_rate_reg_array_size = 12,
-			.csiphy_data_rate_regs = {
-				{0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x9B4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xAB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xBB4, 0x02, 0x01, CSIPHY_DEFAULT_PARAMS},
+			.data_rate_reg_array_size = 4,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x144, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x164, 0x33, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x16C, 0x25, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x9B4, 0x02, 0x01,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x344, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x364, 0x33, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x36C, 0x25, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xAB4, 0x02, 0x01,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x544, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x564, 0x33, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x56C, 0x25, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xBB4, 0x02, 0x01,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
 			},
-		}
-	}
+		},
+	},
 };
-
 #endif /* _CAM_CSIPHY_1_2_1_HWREG_H_ */

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h

@@ -342,56 +342,130 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = {
 		{
 			/* (2.5 * 10**3 * 2.28) rounded value*/
 			.bandwidth = 5700000000,
-			.data_rate_reg_array_size = 6,
-			.csiphy_data_rate_regs = {
-				{0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xBB4, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},
-
-			}
+			.data_rate_reg_array_size = 2,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x144, 0x22, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x9B4, 0x03, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x344, 0x22, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xAB4, 0x03, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x544, 0x22, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xBB4, 0x03, 0x0A,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
 		},
 		{
 			/* (3.5 * 10**3 * 2.28) rounded value */
 			.bandwidth = 7980000000,
-			.data_rate_reg_array_size = 12,
-			.csiphy_data_rate_regs = {
-				{0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xA88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xB88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xA80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xB80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x9B4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xAB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xBB4, 0x02, 0x0A, CSIPHY_DEFAULT_PARAMS},
+			.data_rate_reg_array_size = 4,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x144, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x988, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x980, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x9B4, 0x02, 0x0A,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x344, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xA88, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xA80, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xAB4, 0x02, 0x0A,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x344, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xB88, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xB80, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xBB4, 0x02, 0x0A,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
 			},
 		},
 		{
 			/* (4.5 * 10**3 * 2.28) rounded value */
 			.bandwidth = 10260000000,
-			.data_rate_reg_array_size = 12,
-			.csiphy_data_rate_regs = {
-				{0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xA88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xB88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xA80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xB80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x9B4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xAB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xBB4, 0x01, 0x0A, CSIPHY_DEFAULT_PARAMS},
+			.data_rate_reg_array_size = 4,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x144, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x988, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x980, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x9B4, 0x01, 0x0A,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x344, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xA88, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xA80, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xAB4, 0x01, 0x0A,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x344, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xB88, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xB80, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xBB4, 0x01, 0x0A,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
 			},
-		}
-	}
+		},
+	},
 };
 
 #endif /* _CAM_CSIPHY_1_2_3_HWREG_H_ */

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h

@@ -376,57 +376,135 @@ struct data_rate_settings_t data_rate_delta_table_1_2 = {
 		{
 			/* (2.5 * 10**3 * 2.28) rounded value*/
 			.bandwidth = 5700000000,
-			.data_rate_reg_array_size = 3,
-			.csiphy_data_rate_regs = {
-				{0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
-			}
+			.data_rate_reg_array_size = 1,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x144, 0x22, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x344, 0x22, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x544, 0x22, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
 		},
 		{
 			/* (3.5 * 10**3 * 2.28) rounded value */
 			.bandwidth = 7980000000,
-			.data_rate_reg_array_size = 15,
-			.csiphy_data_rate_regs = {
-				{0x9B4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xAB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xBB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xA88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xA80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xB88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xB80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x10C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x30C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x50C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+			.data_rate_reg_array_size = 5,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x9B4, 0x02, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x144, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x988, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x980, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x10C, 0x08, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0xAB4, 0x02, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x344, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xA88, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xA80, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x30C, 0x08, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0xBB4, 0x02, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x544, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xB88, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xB80, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x50C, 0x08, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
 			},
 		},
 		{
 			/* (4.5 * 10**3 * 2.28) rounded value */
 			.bandwidth = 10260000000,
-			.data_rate_reg_array_size = 15,
-			.csiphy_data_rate_regs = {
-				{0x9B4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xAB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xBB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xA88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xA80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xB88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0xB80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x10C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x30C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x50C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+			.data_rate_reg_array_size = 5,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x9B4, 0x02, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x144, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x988, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x980, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x10C, 0x08, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0xAB4, 0x02, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x344, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xA88, 0x05, 0x00,
+						CSIPHY_DEFAULT_PARAMS},
+						{0xA80, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x30C, 0x08, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0xBB4, 0x02, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x544, 0xB2, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xB88, 0x05, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0xB80, 0x60, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x50C, 0x08, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+					},
+				},
 			},
-		}
-	}
+		},
+	},
 };
 #endif /* _CAM_CSIPHY_1_2_HWREG_H_ */

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -15,7 +15,7 @@ struct csiphy_reg_parms_t csiphy_v2_1_0 = {
 	.csiphy_common_array_size = 6,
 	.csiphy_reset_array_size = 5,
 	.csiphy_2ph_config_array_size = 19,
-	.csiphy_3ph_config_array_size = 28,
+	.csiphy_3ph_config_array_size = 29,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
 };
@@ -286,6 +286,7 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0268, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x026C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0204, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
 		{0x0214, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0260, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0240, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -316,6 +317,7 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0668, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x066C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0604, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
 		{0x0614, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0660, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0640, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -346,6 +348,7 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0A68, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A6C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A04, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
 		{0x0A14, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A60, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A40, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -372,71 +375,106 @@ struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
 		{
 			/* (2.5 * 10**3 * 2.28) rounded value*/
 			.bandwidth = 5700000000,
-			.data_rate_reg_array_size = 9,
-			.csiphy_data_rate_regs = {
-				{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x020C, 0x03, 0x00,
-					CSIPHY_SETTLE_CNT_LOWER_BYTE},
-				{0x0208, 0x00, 0x00,
-					CSIPHY_SETTLE_CNT_HIGHER_BYTE},
-				{0x060C, 0x03, 0x00,
-					CSIPHY_SETTLE_CNT_LOWER_BYTE},
-				{0x0608, 0x00, 0x00,
-					CSIPHY_SETTLE_CNT_HIGHER_BYTE},
-				{0x0A0C, 0x03, 0x00,
-					CSIPHY_SETTLE_CNT_LOWER_BYTE},
-				{0x0A08, 0x00, 0x00,
-					CSIPHY_SETTLE_CNT_HIGHER_BYTE},
-
-			}
+			.data_rate_reg_array_size = 2,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0290, 0x02, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x020C, 0x03, 0x00,
+							CSIPHY_SETTLE_CNT_LOWER_BYTE},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0690, 0x02, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x060C, 0x03, 0x00,
+							CSIPHY_SETTLE_CNT_LOWER_BYTE},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A90, 0x02, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x0A0C, 0x03, 0x00,
+							CSIPHY_SETTLE_CNT_LOWER_BYTE},
+					},
+				},
+			},
 		},
 		{
 			/* (4.5 * 10**3 * 2.28) rounded value */
 			.bandwidth = 10260000000,
-			.data_rate_reg_array_size = 9,
-			.csiphy_data_rate_regs = {
-				{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x020C, 0x03, 0x00,
-					CSIPHY_SETTLE_CNT_LOWER_BYTE},
-				{0x0208, 0x00, 0x00,
-					CSIPHY_SETTLE_CNT_HIGHER_BYTE},
-				{0x060C, 0x03, 0x00,
-					CSIPHY_SETTLE_CNT_LOWER_BYTE},
-				{0x0608, 0x00, 0x00,
-					CSIPHY_SETTLE_CNT_HIGHER_BYTE},
-				{0x0A0C, 0x03, 0x00,
-					CSIPHY_SETTLE_CNT_LOWER_BYTE},
-				{0x0A08, 0x00, 0x00,
-					CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+			.data_rate_reg_array_size = 2,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0290, 0x03, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x020C, 0x03, 0x00,
+							CSIPHY_SETTLE_CNT_LOWER_BYTE},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0690, 0x03, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x060C, 0x03, 0x00,
+							CSIPHY_SETTLE_CNT_LOWER_BYTE},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A90, 0x03, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x0A0C, 0x03, 0x00,
+							CSIPHY_SETTLE_CNT_LOWER_BYTE},
+					},
+				},
 			},
 		},
 		{
 			/* (6.5 * 10**3 * 2.28) rounded value */
 			.bandwidth = 14820000000,
-			.data_rate_reg_array_size = 9,
-			.csiphy_data_rate_regs = {
-				{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
-				{0x020C, 0x07, 0x00,
-					CSIPHY_SETTLE_CNT_LOWER_BYTE},
-				{0x0208, 0x00, 0x00,
-					CSIPHY_SETTLE_CNT_HIGHER_BYTE},
-				{0x060C, 0x07, 0x00,
-					CSIPHY_SETTLE_CNT_LOWER_BYTE},
-				{0x0608, 0x00, 0x00,
-					CSIPHY_SETTLE_CNT_HIGHER_BYTE},
-				{0x0A0C, 0x07, 0x00,
-					CSIPHY_SETTLE_CNT_LOWER_BYTE},
-				{0x0A08, 0x00, 0x00,
-					CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+			.data_rate_reg_array_size = 2,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0290, 0x03, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x020C, 0x07, 0x00,
+							CSIPHY_SETTLE_CNT_LOWER_BYTE},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0690, 0x03, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x060C, 0x07, 0x00,
+							CSIPHY_SETTLE_CNT_LOWER_BYTE},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A90, 0x03, 0x00,
+							CSIPHY_DEFAULT_PARAMS},
+						{0x0A0C, 0x07, 0x00,
+							CSIPHY_SETTLE_CNT_LOWER_BYTE},
+					},
+				},
 			},
-		}
-	}
+		},
+	},
 };
 
-#endif /* _CAM_CSIPHY_2_1_0_HWREG_H_ */
+#endif /* _CAM_CSIPHY_2_1_0_HWREG_H_ */