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@@ -6,21 +6,16 @@
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#ifndef _CPASTOP_V780_100_H_
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#ifndef _CPASTOP_V780_100_H_
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#define _CPASTOP_V780_100_H_
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#define _CPASTOP_V780_100_H_
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-#define TEST_IRQ_ENABLE 0
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-
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static struct cam_camnoc_irq_sbm cam_cpas_v780_100_irq_sbm = {
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static struct cam_camnoc_irq_sbm cam_cpas_v780_100_irq_sbm = {
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.sbm_enable = {
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.sbm_enable = {
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.access_type = CAM_REG_TYPE_READ_WRITE,
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.access_type = CAM_REG_TYPE_READ_WRITE,
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.enable = true,
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.enable = true,
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- .offset = 0x240, /* CAM_NOC_SBM_FAULTINEN0_LOW */
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+ .offset = 0x240, /* CAM_NOC_SBM_FAULTINEN0_LOW */
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.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
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.value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
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- 0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
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- 0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
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+ 0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
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+ 0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
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0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
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0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
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- 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
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- (TEST_IRQ_ENABLE ?
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- 0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */
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- 0x0),
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+ 0x20, /* SBM_FAULTINEN0_LOW_PORT5_MASK */
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},
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},
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.sbm_status = {
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.sbm_status = {
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.access_type = CAM_REG_TYPE_READ,
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.access_type = CAM_REG_TYPE_READ,
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@@ -31,7 +26,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v780_100_irq_sbm = {
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.access_type = CAM_REG_TYPE_WRITE,
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.access_type = CAM_REG_TYPE_WRITE,
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.enable = true,
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.enable = true,
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.offset = 0x280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
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.offset = 0x280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
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- .value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
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+ .value = 0x1,
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}
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}
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};
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};
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@@ -198,13 +193,13 @@ static struct cam_camnoc_irq_err
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},
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},
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{
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{
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.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
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.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
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- .enable = TEST_IRQ_ENABLE ? true : false,
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+ .enable = false,
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.sbm_port = 0x80, /* SBM_FAULTINSTATUS0_LOW_PORT7_MASK */
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.sbm_port = 0x80, /* SBM_FAULTINSTATUS0_LOW_PORT7_MASK */
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.err_enable = {
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.err_enable = {
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.access_type = CAM_REG_TYPE_READ_WRITE,
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.access_type = CAM_REG_TYPE_READ_WRITE,
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.enable = true,
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.enable = true,
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.offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
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.offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
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- .value = 0x5,
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+ .value = 0x3,
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},
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},
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.err_status = {
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.err_status = {
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.access_type = CAM_REG_TYPE_READ,
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.access_type = CAM_REG_TYPE_READ,
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@@ -1206,6 +1201,10 @@ static struct cam_camnoc_info cam780_cpas100_camnoc_info = {
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.irq_err_size = ARRAY_SIZE(cam_cpas_v780_100_irq_err),
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.irq_err_size = ARRAY_SIZE(cam_cpas_v780_100_irq_err),
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.err_logger = &cam780_cpas100_err_logger_offsets,
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.err_logger = &cam780_cpas100_err_logger_offsets,
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.errata_wa_list = &cam780_cpas100_errata_wa_list,
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.errata_wa_list = &cam780_cpas100_errata_wa_list,
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+ .test_irq_info = {
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+ .sbm_enable_mask = 0x80,
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+ .sbm_clear_mask = 0x2,
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+ }
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};
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};
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static struct cam_cpas_camnoc_qchannel cam780_cpas100_qchannel_info = {
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static struct cam_cpas_camnoc_qchannel cam780_cpas100_qchannel_info = {
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