Merge "msm: camera: csiphy: Rearrange the CSIPHY bring up sequence" into camera-kernel.lnx.5.0

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -88,6 +88,114 @@ static void cam_csiphy_reset_phyconfig_param(struct csiphy_device *csiphy_dev,
 	csiphy_dev->csiphy_info[index].hdl_data.device_hdl = -1;
 }
 
+static inline void cam_csiphy_apply_onthego_reg_values(void __iomem *csiphybase, uint8_t csiphy_idx)
+{
+	int                                                      i;
+
+	CAM_DBG(CAM_CSIPHY, "csiphy: %d, onthego_reg_count: %d",
+		csiphy_idx,
+		csiphy_onthego_reg_count);
+
+	if (csiphy_onthego_reg_count % 3)
+		csiphy_onthego_reg_count -= (csiphy_onthego_reg_count % 3);
+
+	for (i = 0; i < csiphy_onthego_reg_count; i += 3) {
+		cam_io_w_mb(csiphy_onthego_regs[i+1],
+			csiphybase + csiphy_onthego_regs[i]);
+
+		if (csiphy_onthego_regs[i+2])
+			usleep_range(csiphy_onthego_regs[i+2], csiphy_onthego_regs[i+2] + 5);
+
+		CAM_INFO(CAM_CSIPHY, "Offset: 0x%x, Val: 0x%x Delay(us): %u",
+			csiphy_onthego_regs[i],
+			cam_io_r_mb(csiphybase + csiphy_onthego_regs[i]),
+			csiphy_onthego_regs[i+2]);
+	}
+}
+
+static inline int cam_csiphy_release_from_reset_state(struct csiphy_device *csiphy_dev,
+	void __iomem *csiphybase, int32_t instance)
+{
+	int                                                  i;
+	struct csiphy_reg_parms_t                           *csiphy_reg;
+	struct csiphy_reg_t                                 *csiphy_reset_release_reg;
+	bool                                                 config_found = false;
+
+	if (!csiphy_dev || !csiphybase) {
+		CAM_ERR(CAM_CSIPHY, "Invalid input params: csiphy_dev: %p, csiphybase: %p",
+			csiphy_dev, csiphybase);
+		return -EINVAL;
+	}
+
+	CAM_DBG(CAM_CSIPHY, "Csiphy idx: %d", csiphy_dev->soc_info.index);
+
+	csiphy_reg = &csiphy_dev->ctrl_reg->csiphy_reg;
+	for (i = 0; i < csiphy_reg->csiphy_reset_exit_array_size; i++) {
+		csiphy_reset_release_reg = &csiphy_dev->ctrl_reg->csiphy_reset_exit_regs[i];
+
+		switch (csiphy_reset_release_reg->csiphy_param_type) {
+		case CSIPHY_2PH_REGS:
+			if (!g_phy_data[csiphy_dev->soc_info.index].is_3phase &&
+				!csiphy_dev->combo_mode &&
+				!csiphy_dev->cphy_dphy_combo_mode) {
+				cam_io_w_mb(csiphy_reset_release_reg->reg_data,
+					csiphybase + csiphy_reset_release_reg->reg_addr);
+				config_found = true;
+			}
+			break;
+		case CSIPHY_3PH_REGS:
+			if (g_phy_data[csiphy_dev->soc_info.index].is_3phase &&
+				!csiphy_dev->combo_mode  &&
+				!csiphy_dev->cphy_dphy_combo_mode) {
+				cam_io_w_mb(csiphy_reset_release_reg->reg_data,
+					csiphybase + csiphy_reset_release_reg->reg_addr);
+				config_found = true;
+			}
+			break;
+		case CSIPHY_2PH_COMBO_REGS:
+			if (!csiphy_dev->csiphy_info[instance].csiphy_3phase &&
+					csiphy_dev->combo_mode &&
+					!csiphy_dev->cphy_dphy_combo_mode) {
+				cam_io_w_mb(csiphy_reset_release_reg->reg_data,
+					csiphybase + csiphy_reset_release_reg->reg_addr);
+				config_found = true;
+			}
+			break;
+		case CSIPHY_3PH_COMBO_REGS:
+			if (csiphy_dev->csiphy_info[instance].csiphy_3phase &&
+					csiphy_dev->combo_mode &&
+					!csiphy_dev->cphy_dphy_combo_mode) {
+				cam_io_w_mb(csiphy_reset_release_reg->reg_data,
+					csiphybase + csiphy_reset_release_reg->reg_addr);
+				config_found = true;
+			}
+			break;
+		case CSIPHY_2PH_3PH_COMBO_REGS:
+			if (!csiphy_dev->combo_mode && csiphy_dev->cphy_dphy_combo_mode) {
+				cam_io_w_mb(csiphy_reset_release_reg->reg_data,
+					csiphybase + csiphy_reset_release_reg->reg_addr);
+				config_found = true;
+			}
+			break;
+		default:
+			CAM_ERR(CAM_CSIPHY, "Invalid combination");
+			return -EINVAL;
+			break;
+		}
+
+		if (config_found) {
+			if (csiphy_reset_release_reg->delay) {
+				usleep_range(csiphy_reset_release_reg->delay,
+					csiphy_reset_release_reg->delay + 5);
+			}
+
+			break;
+		}
+	}
+
+	return 0;
+}
+
 void cam_csiphy_query_cap(struct csiphy_device *csiphy_dev,
 	struct cam_csiphy_query_cap *csiphy_cap)
 {
@@ -174,20 +282,20 @@ void cam_csiphy_reset(struct csiphy_device *csiphy_dev)
 	int32_t  i;
 	void __iomem *base = NULL;
 	uint32_t size =
-		csiphy_dev->ctrl_reg->csiphy_reg.csiphy_reset_array_size;
+		csiphy_dev->ctrl_reg->csiphy_reg.csiphy_reset_enter_array_size;
 	struct cam_hw_soc_info *soc_info = &csiphy_dev->soc_info;
 
 	base = soc_info->reg_map[0].mem_base;
 
 	for (i = 0; i < size; i++) {
 		cam_io_w_mb(
-			csiphy_dev->ctrl_reg->csiphy_reset_reg[i].reg_data,
+			csiphy_dev->ctrl_reg->csiphy_reset_enter_regs[i].reg_data,
 			base +
-			csiphy_dev->ctrl_reg->csiphy_reset_reg[i].reg_addr);
-		if (csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay > 0)
+			csiphy_dev->ctrl_reg->csiphy_reset_enter_regs[i].reg_addr);
+		if (csiphy_dev->ctrl_reg->csiphy_reset_enter_regs[i].delay > 0)
 			usleep_range(
-			csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay,
-			csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay
+			csiphy_dev->ctrl_reg->csiphy_reset_enter_regs[i].delay,
+			csiphy_dev->ctrl_reg->csiphy_reset_enter_regs[i].delay
 			+ 5);
 	}
 
@@ -1050,6 +1158,7 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev,
 				CAM_DBG(CAM_CSIPHY, "Do Nothing");
 			break;
 			}
+
 			if (reg_array[lane_pos][i].delay > 0) {
 				usleep_range(reg_array[lane_pos][i].delay,
 					reg_array[lane_pos][i].delay + 5);
@@ -1189,11 +1298,9 @@ static int cam_csiphy_update_lane(
 
 	for (i = 0; i < size; i++) {
 		csiphy_common_reg = &csiphy->ctrl_reg->csiphy_common_reg[i];
-		switch (csiphy_common_reg->csiphy_param_type) {
-		case CSIPHY_LANE_ENABLE:
+		if (csiphy_common_reg->csiphy_param_type == CSIPHY_LANE_ENABLE) {
 			CAM_DBG(CAM_CSIPHY, "LANE_ENABLE: %d", lane_enable);
-			lane_enable = cam_io_r(base_address +
-				csiphy_common_reg->reg_addr);
+			lane_enable = cam_io_r(base_address + csiphy_common_reg->reg_addr);
 			break;
 		}
 	}
@@ -1207,21 +1314,16 @@ static int cam_csiphy_update_lane(
 
 	CAM_DBG(CAM_CSIPHY, "lane_assign: 0x%x, lane_enable: 0x%x",
 		lane_assign, lane_enable);
-	for (i = 0; i < size; i++) {
-		csiphy_common_reg = &csiphy->ctrl_reg->csiphy_common_reg[i];
-		switch (csiphy_common_reg->csiphy_param_type) {
-		case CSIPHY_LANE_ENABLE:
-			CAM_DBG(CAM_CSIPHY, "LANE_ENABLE: %d", lane_enable);
-			cam_io_w_mb(lane_enable,
-				base_address + csiphy_common_reg->reg_addr);
-			if (csiphy_common_reg->delay)
-				usleep_range(csiphy_common_reg->delay,
-					csiphy_common_reg->delay + 5);
-			break;
-		}
+
+	if (csiphy_common_reg->csiphy_param_type == CSIPHY_LANE_ENABLE) {
+		cam_io_w_mb(lane_enable, base_address + csiphy_common_reg->reg_addr);
+		if (csiphy_common_reg->delay)
+			usleep_range(csiphy_common_reg->delay, csiphy_common_reg->delay + 5);
+
+		return 0;
 	}
 
-	return 0;
+	return -EINVAL;
 }
 
 static int __csiphy_cpas_configure_for_main_or_aon(
@@ -2031,52 +2133,34 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 		if (rc < 0) {
 			CAM_ERR(CAM_CSIPHY, "cam_csiphy_config_dev failed");
 			cam_csiphy_disable_hw(csiphy_dev);
-			goto cpas_stop;
+			goto hw_cnt_decrement;
 		}
 
-		if (csiphy_onthego_reg_count) {
-			CAM_DBG(CAM_CSIPHY, "csiphy_onthego_reg_count: %d",
-				csiphy_onthego_reg_count);
+		if (csiphy_onthego_reg_count)
+			cam_csiphy_apply_onthego_reg_values(csiphybase, soc_info->index);
 
-			if (csiphy_onthego_reg_count % 3)
-				csiphy_onthego_reg_count -= (csiphy_onthego_reg_count % 3);
-
-			for (i = 0; i < csiphy_onthego_reg_count; i += 3) {
-				cam_io_w_mb(csiphy_onthego_regs[i+1],
-					csiphybase + csiphy_onthego_regs[i]);
-
-				if (csiphy_onthego_regs[i+2])
-					usleep_range(csiphy_onthego_regs[i+2],
-						csiphy_onthego_regs[i+2] + 5);
-
-				CAM_INFO(CAM_CSIPHY, "Offset: 0x%x, Val: 0x%x Delay(us): %u",
-					csiphy_onthego_regs[i],
-					cam_io_r_mb(csiphybase + csiphy_onthego_regs[i]),
-					csiphy_onthego_regs[i+2]);
-			}
-		}
+		cam_csiphy_release_from_reset_state(csiphy_dev, csiphybase, offset);
 
 		if (g_phy_data[csiphy_dev->soc_info.index].is_3phase && status_reg_ptr) {
-			rc = 0;
 			for (i = 0; i < CAM_CSIPHY_MAX_CPHY_LANES; i++) {
 				if (status_reg_ptr->cphy_lane_status[i]) {
 					cphy_trio_status = cam_io_r_mb(csiphybase +
 						status_reg_ptr->cphy_lane_status[i]);
 
-					if (cphy_trio_status) {
-						CAM_ERR(CAM_CSIPHY,
+					cphy_trio_status &= 0x1F;
+					if (cphy_trio_status == 0 || cphy_trio_status == 8) {
+						CAM_DBG(CAM_CSIPHY,
+							"Reg_offset: 0x%x, cphy_trio%d_status = 0x%x",
+							status_reg_ptr->cphy_lane_status[i],
+							i, cphy_trio_status);
+					} else {
+						CAM_WARN(CAM_CSIPHY,
 							"Reg_offset: 0x%x, Cphy_trio%d_status = 0x%x",
 							status_reg_ptr->cphy_lane_status[i],
 							i, cphy_trio_status);
-						rc = -EINVAL;
 					}
 				}
 			}
-
-			if (rc) {
-				cam_csiphy_disable_hw(csiphy_dev);
-				goto cpas_stop;
-			}
 		}
 
 		if (csiphy_dev->en_full_phy_reg_dump)
@@ -2144,6 +2228,13 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 	mutex_unlock(&csiphy_dev->mutex);
 	return rc;
 
+hw_cnt_decrement:
+	if (csiphy_reg->prgm_cmn_reg_across_csiphy) {
+		mutex_lock(&active_csiphy_cnt_mutex);
+		active_csiphy_hw_cnt--;
+		mutex_unlock(&active_csiphy_cnt_mutex);
+	}
+
 cpas_stop:
 	if (cam_csiphy_cpas_ops(csiphy_dev->cpas_handle, false))
 		CAM_ERR(CAM_CSIPHY, "cpas stop failed");

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

@@ -48,6 +48,9 @@
 #define CSIPHY_2PH_REGS                  5
 #define CSIPHY_3PH_REGS                  6
 #define CSIPHY_SKEW_CAL                  7
+#define CSIPHY_2PH_COMBO_REGS            8
+#define CSIPHY_3PH_COMBO_REGS            9
+#define CSIPHY_2PH_3PH_COMBO_REGS        10
 
 #define CSIPHY_MAX_INSTANCES_PER_PHY     3
 
@@ -111,7 +114,8 @@ struct cam_cphy_dphy_status_reg_params_t {
  * @mipi_csiphy_interrupt_clear0_addr : CSIPhy interrupt clear addr
  * @csiphy_version                    : CSIPhy Version
  * @csiphy_common_array_size          : CSIPhy common array size
- * @csiphy_reset_array_size           : CSIPhy reset array size
+ * @csiphy_reset_enter_array_size     : CSIPhy reset array size
+ * @csiphy_reset_exit_array_size      : CSIPhy reset release array size
  * @csiphy_2ph_config_array_size      : 2ph settings size
  * @csiphy_3ph_config_array_size      : 3ph settings size
  * @csiphy_cpas_cp_bits_per_phy       : CP bits per phy
@@ -136,7 +140,8 @@ struct csiphy_reg_parms_t {
 	uint32_t csiphy_version;
 	uint32_t csiphy_interrupt_status_size;
 	uint32_t csiphy_common_array_size;
-	uint32_t csiphy_reset_array_size;
+	uint32_t csiphy_reset_enter_array_size;
+	uint32_t csiphy_reset_exit_array_size;
 	uint32_t csiphy_2ph_config_array_size;
 	uint32_t csiphy_3ph_config_array_size;
 	uint32_t csiphy_2ph_3ph_config_array_size;
@@ -220,7 +225,8 @@ struct bist_reg_settings_t {
  * struct csiphy_ctrl_t
  * @csiphy_reg                : Register address
  * @csiphy_common_reg         : Common register set
- * @csiphy_reset_reg          : Reset register set
+ * @csiphy_reset_enter_regs   : Reset register set
+ * @csiphy_reset_exit_regs    : Reset release registers
  * @csiphy_2ph_reg            : 2phase register set
  * @csiphy_2ph_combo_mode_reg : 2phase combo register set
  * @csiphy_3ph_reg            : 3phase register set
@@ -234,7 +240,8 @@ struct csiphy_ctrl_t {
 	struct csiphy_reg_parms_t csiphy_reg;
 	struct csiphy_reg_t *csiphy_common_reg;
 	struct csiphy_reg_t *csiphy_irq_reg;
-	struct csiphy_reg_t *csiphy_reset_reg;
+	struct csiphy_reg_t *csiphy_reset_enter_regs;
+	struct csiphy_reg_t *csiphy_reset_exit_regs;
 	struct csiphy_reg_t (*csiphy_2ph_reg)[MAX_SETTINGS_PER_LANE];
 	struct csiphy_reg_t (*csiphy_2ph_combo_mode_reg)[MAX_SETTINGS_PER_LANE];
 	struct csiphy_reg_t (*csiphy_3ph_reg)[MAX_SETTINGS_PER_LANE];

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

@@ -270,14 +270,13 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 	if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.0")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_0_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-				csiphy_2ph_v1_0_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v1_0_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_0_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg =
-				csiphy_3ph_v1_0_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = csiphy_3ph_v1_0_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_0;
 		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_0;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_1_0;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_1_0;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_0;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V10;
@@ -287,16 +286,13 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.1")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_1_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v1_1_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v1_1_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_1_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg =
-			csiphy_3ph_v1_1_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = csiphy_3ph_v1_1_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_1;
-		csiphy_dev->ctrl_reg->csiphy_common_reg =
-			csiphy_common_reg_1_1;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg =
-			csiphy_reset_reg_1_1;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_1;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_1_1;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_1;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
 		csiphy_dev->is_divisor_32_comp = false;
@@ -306,130 +302,110 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.2")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v1_2_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v1_2_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2;
-		csiphy_dev->ctrl_reg->csiphy_common_reg =
-			csiphy_common_reg_1_2;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg =
-			csiphy_reset_reg_1_2;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_2;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_1_2;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2;
 		csiphy_dev->is_divisor_32_comp = true;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V12;
 		csiphy_dev->clk_lane = 0;
-		csiphy_dev->ctrl_reg->data_rates_settings_table =
-			&data_rate_delta_table_1_2;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_1_2;
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.2.1")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_1_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v1_2_1_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v1_2_1_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_1_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2_1;
-		csiphy_dev->ctrl_reg->csiphy_common_reg =
-			csiphy_common_reg_1_2_1;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg =
-			csiphy_reset_reg_1_2_1;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_2_1;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_1_2_1;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_1;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;
 		csiphy_dev->is_divisor_32_comp = true;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V121;
 		csiphy_dev->clk_lane = 0;
-		csiphy_dev->ctrl_reg->data_rates_settings_table =
-			&data_rate_delta_table_1_2_1;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_1_2_1;
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.2.2")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v1_2_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v1_2_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2;
-		csiphy_dev->ctrl_reg->csiphy_common_reg =
-			csiphy_common_reg_1_2;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg =
-			csiphy_reset_reg_1_2;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_2;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_1_2;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2;
 		csiphy_dev->is_divisor_32_comp = false;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V12;
 		csiphy_dev->clk_lane = 0;
-		csiphy_dev->ctrl_reg->data_rates_settings_table =
-			&data_rate_delta_table_1_2;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_1_2;
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.2.2.2")) {
 		/* settings for lito v2 */
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v1_2_2_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v1_2_2_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2;
-		csiphy_dev->ctrl_reg->csiphy_common_reg =
-			csiphy_common_reg_1_2_2;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg =
-			csiphy_reset_reg_1_2;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_2_2;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_1_2;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_2;
 		csiphy_dev->is_divisor_32_comp = false;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V12;
 		csiphy_dev->clk_lane = 0;
-		csiphy_dev->ctrl_reg->data_rates_settings_table =
-			&data_rate_delta_table_1_2;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_1_2;
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.2.3")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_3_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v1_2_3_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v1_2_3_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_3_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2_3;
-		csiphy_dev->ctrl_reg->csiphy_common_reg =
-			csiphy_common_reg_1_2_3;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg =
-			csiphy_reset_reg_1_2_3;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_2_3;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_1_2_3;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_3;
 		csiphy_dev->is_divisor_32_comp = true;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V123;
 		csiphy_dev->clk_lane = 0;
-		csiphy_dev->ctrl_reg->data_rates_settings_table =
-			&data_rate_delta_table_1_2_3;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_1_2_3;
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.2.4")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_3_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v1_2_3_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v1_2_3_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_3_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2_3;
-		csiphy_dev->ctrl_reg->csiphy_common_reg =
-			csiphy_common_reg_1_2_3;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg =
-			csiphy_reset_reg_1_2_3;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_2_3;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_1_2_3;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_3;
 		csiphy_dev->is_divisor_32_comp = true;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V124;
 		csiphy_dev->clk_lane = 0;
-		csiphy_dev->ctrl_reg->data_rates_settings_table =
-			&data_rate_delta_table_1_2_3;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_1_2_3;
 	}  else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.2.5")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_5_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v1_2_5_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v1_2_5_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_5_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2_5;
-		csiphy_dev->ctrl_reg->csiphy_common_reg =
-			csiphy_common_reg_1_2_5;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg =
-			csiphy_reset_reg_1_2_5;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_1_2_5;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_1_2_5;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_5;
 		csiphy_dev->is_divisor_32_comp = false;
@@ -439,13 +415,13 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v2.0")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v2_0_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v2_0_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_0_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_0;
 		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_0;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_2_0;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_2_0;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_0;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V20;
@@ -455,13 +431,13 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v2.0.1")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v2_0_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v2_0_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_0_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_0;
 		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_0;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_2_0;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_reg_2_0;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = NULL;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_0;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V201;
@@ -471,21 +447,19 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 	} else if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v2.1.0")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_1_0_reg;
-		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
-			csiphy_2ph_v2_1_0_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v2_1_0_combo_mode_reg;
 		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_1_0_reg;
 		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
 		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_1_0;
-		csiphy_dev->ctrl_reg->csiphy_common_reg =
-			csiphy_common_reg_2_1_0;
-		csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_2_1_0;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_1_0;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_enter_reg_2_1_0;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = csiphy_reset_exit_reg_2_1_0;
 		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_1_0;
 		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;
 		csiphy_dev->hw_version = CSIPHY_VERSION_V210;
 		csiphy_dev->is_divisor_32_comp = true;
 		csiphy_dev->clk_lane = 0;
-		csiphy_dev->ctrl_reg->data_rates_settings_table =
-			&data_rate_delta_table_2_1_0;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_1_0;
 		csiphy_dev->ctrl_reg->csiphy_bist_reg = &bist_setting_2_1_0;
 	} else {
 		CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x",

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h

@@ -16,7 +16,8 @@ struct csiphy_reg_parms_t csiphy_v1_0 = {
 	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 5,
-	.csiphy_reset_array_size = 5,
+	.csiphy_reset_enter_array_size = 5,
+	.csiphy_reset_exit_array_size = 0,
 	.csiphy_2ph_config_array_size = 14,
 	.csiphy_3ph_config_array_size = 19,
 	.aon_sel_params = NULL,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h

@@ -16,7 +16,8 @@ struct csiphy_reg_parms_t csiphy_v1_1 = {
 	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 5,
-	.csiphy_reset_array_size = 5,
+	.csiphy_reset_enter_array_size = 5,
+	.csiphy_reset_exit_array_size = 0,
 	.csiphy_2ph_config_array_size = 14,
 	.csiphy_3ph_config_array_size = 43,
 	.csiphy_2ph_clock_lane = 0x1,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h

@@ -16,7 +16,8 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = {
 	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 7,
-	.csiphy_reset_array_size = 5,
+	.csiphy_reset_enter_array_size = 5,
+	.csiphy_reset_exit_array_size = 0,
 	.csiphy_2ph_config_array_size = 20,
 	.csiphy_3ph_config_array_size = 33,
 	.csiphy_2ph_clock_lane = 0x1,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h

@@ -16,7 +16,8 @@ struct csiphy_reg_parms_t csiphy_v1_2_2 = {
 	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 8,
-	.csiphy_reset_array_size = 5,
+	.csiphy_reset_enter_array_size = 5,
+	.csiphy_reset_exit_array_size = 0,
 	.csiphy_2ph_config_array_size = 18,
 	.csiphy_3ph_config_array_size = 33,
 	.csiphy_2ph_clock_lane = 0x1,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h

@@ -16,7 +16,8 @@ struct csiphy_reg_parms_t csiphy_v1_2_3 = {
 	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 5,
-	.csiphy_reset_array_size = 2,
+	.csiphy_reset_enter_array_size = 2,
+	.csiphy_reset_exit_array_size = 0,
 	.csiphy_2ph_config_array_size = 16,
 	.csiphy_3ph_config_array_size = 31,
 	.csiphy_2ph_3ph_config_array_size = 0,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_5_hwreg.h

@@ -16,7 +16,8 @@ struct csiphy_reg_parms_t csiphy_v1_2_5 = {
 	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 6,
-	.csiphy_reset_array_size = 5,
+	.csiphy_reset_enter_array_size = 5,
+	.csiphy_reset_exit_array_size = 0,
 	.csiphy_2ph_config_array_size = 21,
 	.csiphy_3ph_config_array_size = 30,
 	.csiphy_2ph_clock_lane = 0x1,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h

@@ -16,7 +16,8 @@ struct csiphy_reg_parms_t csiphy_v1_2 = {
 	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 7,
-	.csiphy_reset_array_size = 5,
+	.csiphy_reset_enter_array_size = 5,
+	.csiphy_reset_exit_array_size = 0,
 	.csiphy_2ph_config_array_size = 18,
 	.csiphy_3ph_config_array_size = 33,
 	.csiphy_2ph_clock_lane = 0x1,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h

@@ -16,7 +16,8 @@ struct csiphy_reg_parms_t csiphy_v2_0 = {
 	.size_offset_betn_lanes = 0x200,
 	.csiphy_interrupt_status_size = 11,
 	.csiphy_common_array_size = 8,
-	.csiphy_reset_array_size = 5,
+	.csiphy_reset_enter_array_size = 5,
+	.csiphy_reset_exit_array_size = 0,
 	.csiphy_2ph_config_array_size = 15,
 	.csiphy_3ph_config_array_size = 17,
 	.csiphy_2ph_clock_lane = 0x1,

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -29,9 +29,10 @@ struct csiphy_reg_parms_t csiphy_v2_1_0 = {
 	.mipi_csiphy_interrupt_clear0_addr = 0x1058,
 	.mipi_csiphy_glbl_irq_cmd_addr = 0x1028,
 	.csiphy_common_array_size = 4,
-	.csiphy_reset_array_size = 2,
-	.csiphy_2ph_config_array_size = 24,
-	.csiphy_3ph_config_array_size = 43,
+	.csiphy_reset_enter_array_size = 2,
+	.csiphy_reset_exit_array_size = 3,
+	.csiphy_2ph_config_array_size = 23,
+	.csiphy_3ph_config_array_size = 38,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
 	.csiphy_interrupt_status_size = 11,
@@ -46,11 +47,17 @@ struct csiphy_reg_t csiphy_common_reg_2_1_0[] = {
 	{0x101C, 0x7A, 0x00, CSIPHY_DEFAULT_PARAMS},
 };
 
-struct csiphy_reg_t csiphy_reset_reg_2_1_0[] = {
+struct csiphy_reg_t csiphy_reset_enter_reg_2_1_0[] = {
 	{0x1014, 0x00, 0x00, CSIPHY_LANE_ENABLE},
 	{0x1000, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},
 };
 
+struct csiphy_reg_t csiphy_reset_exit_reg_2_1_0[] = {
+	{0x1000, 0x02, 0x00, CSIPHY_2PH_REGS},
+	{0x1000, 0x00, 0x00, CSIPHY_2PH_COMBO_REGS},
+	{0x1000, 0x0E, 0xBE8, CSIPHY_3PH_REGS},
+};
+
 struct csiphy_reg_t csiphy_irq_reg_2_1_0[] = {
 	{0x102c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x1030, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -90,7 +97,6 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL},
 		{0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL},
 		{0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
-		{0x1000, 0x02, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
 		{0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -116,7 +122,6 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 		{0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 		{0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
-		{0x1000, 0x02, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
 		{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -142,7 +147,6 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL},
 		{0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL},
 		{0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
-		{0x1000, 0x02, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
 		{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -168,7 +172,6 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL},
 		{0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL},
 		{0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
-		{0x1000, 0x02, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
 		{0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -194,7 +197,6 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0C5C, 0x00, 0x00, CSIPHY_SKEW_CAL},
 		{0x0C60, 0xBD, 0x00, CSIPHY_SKEW_CAL},
 		{0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL},
-		{0x1000, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
 	},
 };
 
@@ -224,7 +226,6 @@ struct csiphy_reg_t
 		{0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL},
 		{0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL},
 		{0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
-		{0x1000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
 		{0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -250,7 +251,6 @@ struct csiphy_reg_t
 		{0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 		{0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 		{0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
-		{0x1000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
 		{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -276,7 +276,6 @@ struct csiphy_reg_t
 		{0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL},
 		{0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL},
 		{0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
-		{0x1000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
 		{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -302,7 +301,6 @@ struct csiphy_reg_t
 		{0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL},
 		{0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL},
 		{0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
-		{0x1000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
 		{0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -328,16 +326,11 @@ struct csiphy_reg_t
 		{0x0C5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 		{0x0C60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
 		{0x0C64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
-		{0x1000, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	},
 };
 
 struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 	{
-		{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0288, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x028C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0268, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
 		{0x0294, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x02F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -376,13 +369,8 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x024C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0240, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0260, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x1000, 0x0E, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
-		{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0688, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x068C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0668, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
 		{0x0694, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x06F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -421,13 +409,8 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x064C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0640, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0660, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x1000, 0x0E, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
-		{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A88, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A8C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A68, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
 		{0x0A94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0AF4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -466,7 +449,6 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0A4C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A40, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A60, 0xA8, 0x64, CSIPHY_DEFAULT_PARAMS},
-		{0x1000, 0x0E, 0x3E8, CSIPHY_DEFAULT_PARAMS},
 	},
 };
 
@@ -528,27 +510,39 @@ struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
 		{
 			/* ((1 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
 			.bandwidth = 2280000000,
-			.data_rate_reg_array_size = 2,
+			.data_rate_reg_array_size = 6,
 			.per_lane_info = {
 				{
 					.lane_identifier = CPHY_LANE_0,
 					.csiphy_data_rate_regs = {
-						{0x0278, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
-						{0x0214, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 					},
 				},
 				{
 					.lane_identifier = CPHY_LANE_1,
 					.csiphy_data_rate_regs = {
-						{0x0678, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
-						{0x0614, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 					},
 				},
 				{
 					.lane_identifier = CPHY_LANE_2,
 					.csiphy_data_rate_regs = {
-						{0x0A78, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
-						{0x0A14, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
 					},
 				},
 			},
@@ -556,26 +550,38 @@ struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
 		{
 			/* ((2 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
 			.bandwidth = 4560000000,
-			.data_rate_reg_array_size = 2,
+			.data_rate_reg_array_size = 6,
 			.per_lane_info = {
 				{
 					.lane_identifier = CPHY_LANE_0,
 					.csiphy_data_rate_regs = {
-						{0x0278, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0214, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 					},
 				},
 				{
 					.lane_identifier = CPHY_LANE_1,
 					.csiphy_data_rate_regs = {
-						{0x0678, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0614, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 					},
 				},
 				{
 					.lane_identifier = CPHY_LANE_2,
 					.csiphy_data_rate_regs = {
-						{0x0A78, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
 						{0x0A14, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 					},
 				},
@@ -584,27 +590,39 @@ struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
 		{
 			/* ((3.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
 			.bandwidth = 7980000000,
-			.data_rate_reg_array_size = 2,
+			.data_rate_reg_array_size = 6,
 			.per_lane_info = {
 				{
 					.lane_identifier = CPHY_LANE_0,
 					.csiphy_data_rate_regs = {
-						{0x0278, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
-						{0x0214, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x13, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 					},
 				},
 				{
 					.lane_identifier = CPHY_LANE_1,
 					.csiphy_data_rate_regs = {
-						{0x0678, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
-						{0x0614, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x13, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 					},
 				},
 				{
 					.lane_identifier = CPHY_LANE_2,
 					.csiphy_data_rate_regs = {
-						{0x0A78, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
-						{0x0A14, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x13, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 					},
 				},
 			},