disp: msm: dsi: remove unsupported Controller HW
Removes files and version checks for unsupported DSI Controller HW versions. Change-Id: Ic0acd34959ddfcf2db79102857e15f4e06da1d3a Signed-off-by: Michael Ru <mru@codeaurora.org>
This commit is contained in:
Michael Ru
@@ -190,8 +190,6 @@ msm_drm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi_phy.o \
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dsi/dsi_pll.o \
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dsi/dsi_pll_5nm.o \
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dsi/dsi_ctrl_hw_cmn.o \
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dsi/dsi_ctrl_hw_1_4.o \
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dsi/dsi_ctrl_hw_2_0.o \
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dsi/dsi_ctrl_hw_2_2.o \
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dsi/dsi_ctrl.o \
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dsi/dsi_catalog.o \
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@@ -67,45 +67,6 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl,
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ctrl->ops.vid_engine_busy = dsi_ctrl_hw_cmn_vid_engine_busy;
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switch (version) {
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case DSI_CTRL_VERSION_1_4:
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ctrl->ops.setup_lane_map = dsi_ctrl_hw_14_setup_lane_map;
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ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_cmn_ulps_request;
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ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_cmn_ulps_exit;
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ctrl->ops.wait_for_lane_idle =
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dsi_ctrl_hw_14_wait_for_lane_idle;
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ctrl->ops.ulps_ops.get_lanes_in_ulps =
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dsi_ctrl_hw_cmn_get_lanes_in_ulps;
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ctrl->ops.clamp_enable = dsi_ctrl_hw_14_clamp_enable;
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ctrl->ops.clamp_disable = dsi_ctrl_hw_14_clamp_disable;
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ctrl->ops.reg_dump_to_buffer =
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dsi_ctrl_hw_14_reg_dump_to_buffer;
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ctrl->ops.schedule_dma_cmd = NULL;
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ctrl->ops.kickoff_command_non_embedded_mode = NULL;
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ctrl->ops.config_clk_gating = NULL;
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ctrl->ops.configure_cmddma_window = NULL;
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ctrl->ops.reset_trig_ctrl = NULL;
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ctrl->ops.log_line_count = NULL;
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ctrl->ops.splitlink_cmd_setup = NULL;
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break;
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case DSI_CTRL_VERSION_2_0:
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ctrl->ops.setup_lane_map = dsi_ctrl_hw_20_setup_lane_map;
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ctrl->ops.wait_for_lane_idle =
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dsi_ctrl_hw_20_wait_for_lane_idle;
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ctrl->ops.reg_dump_to_buffer =
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dsi_ctrl_hw_20_reg_dump_to_buffer;
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ctrl->ops.ulps_ops.ulps_request = NULL;
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ctrl->ops.ulps_ops.ulps_exit = NULL;
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ctrl->ops.ulps_ops.get_lanes_in_ulps = NULL;
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ctrl->ops.clamp_enable = NULL;
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ctrl->ops.clamp_disable = NULL;
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ctrl->ops.schedule_dma_cmd = NULL;
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ctrl->ops.kickoff_command_non_embedded_mode = NULL;
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ctrl->ops.config_clk_gating = NULL;
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ctrl->ops.configure_cmddma_window = NULL;
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ctrl->ops.reset_trig_ctrl = NULL;
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ctrl->ops.log_line_count = NULL;
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ctrl->ops.splitlink_cmd_setup = NULL;
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break;
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case DSI_CTRL_VERSION_2_2:
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case DSI_CTRL_VERSION_2_3:
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case DSI_CTRL_VERSION_2_4:
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@@ -173,10 +134,6 @@ int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl,
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set_bit(DSI_CTRL_DPHY, ctrl->feature_map);
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switch (version) {
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case DSI_CTRL_VERSION_1_4:
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dsi_catalog_cmn_init(ctrl, version);
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break;
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case DSI_CTRL_VERSION_2_0:
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case DSI_CTRL_VERSION_2_2:
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case DSI_CTRL_VERSION_2_3:
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case DSI_CTRL_VERSION_2_4:
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@@ -49,8 +49,6 @@ struct dsi_ctrl_list_item {
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static LIST_HEAD(dsi_ctrl_list);
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static DEFINE_MUTEX(dsi_ctrl_list_lock);
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static const enum dsi_ctrl_version dsi_ctrl_v1_4 = DSI_CTRL_VERSION_1_4;
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static const enum dsi_ctrl_version dsi_ctrl_v2_0 = DSI_CTRL_VERSION_2_0;
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static const enum dsi_ctrl_version dsi_ctrl_v2_2 = DSI_CTRL_VERSION_2_2;
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static const enum dsi_ctrl_version dsi_ctrl_v2_3 = DSI_CTRL_VERSION_2_3;
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static const enum dsi_ctrl_version dsi_ctrl_v2_4 = DSI_CTRL_VERSION_2_4;
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@@ -58,14 +56,6 @@ static const enum dsi_ctrl_version dsi_ctrl_v2_5 = DSI_CTRL_VERSION_2_5;
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static const enum dsi_ctrl_version dsi_ctrl_v2_6 = DSI_CTRL_VERSION_2_6;
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static const struct of_device_id msm_dsi_of_match[] = {
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{
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.compatible = "qcom,dsi-ctrl-hw-v1.4",
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.data = &dsi_ctrl_v1_4,
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},
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{
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.compatible = "qcom,dsi-ctrl-hw-v2.0",
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.data = &dsi_ctrl_v2_0,
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},
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{
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.compatible = "qcom,dsi-ctrl-hw-v2.2",
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.data = &dsi_ctrl_v2_2,
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@@ -708,18 +698,6 @@ static int dsi_ctrl_init_regmap(struct platform_device *pdev,
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DSI_CTRL_DEBUG(ctrl, "map dsi_ctrl registers to %pK\n", ctrl->hw.base);
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switch (ctrl->version) {
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case DSI_CTRL_VERSION_1_4:
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case DSI_CTRL_VERSION_2_0:
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ptr = msm_ioremap(pdev, "mmss_misc", ctrl->name);
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if (IS_ERR(ptr)) {
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DSI_CTRL_ERR(ctrl, "mmss_misc base address not found\n");
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rc = PTR_ERR(ptr);
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return rc;
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}
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ctrl->hw.mmss_misc_base = ptr;
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ctrl->hw.disp_cc_base = NULL;
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ctrl->hw.mdp_intf_base = NULL;
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break;
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case DSI_CTRL_VERSION_2_2:
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case DSI_CTRL_VERSION_2_3:
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case DSI_CTRL_VERSION_2_4:
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@@ -1273,46 +1251,6 @@ int dsi_ctrl_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl *dsi_ctrl)
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return rc;
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}
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static void dsi_ctrl_wait_for_video_done(struct dsi_ctrl *dsi_ctrl)
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{
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u32 v_total = 0, v_blank = 0, sleep_ms = 0, fps = 0, ret;
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struct dsi_mode_info *timing;
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/**
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* No need to wait if the panel is not video mode or
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* if DSI controller supports command DMA scheduling or
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* if we are sending init commands.
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*/
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if ((dsi_ctrl->host_config.panel_mode != DSI_OP_VIDEO_MODE) ||
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(dsi_ctrl->version >= DSI_CTRL_VERSION_2_2) ||
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(dsi_ctrl->current_state.vid_engine_state !=
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DSI_CTRL_ENGINE_ON))
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return;
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dsi_ctrl->hw.ops.clear_interrupt_status(&dsi_ctrl->hw,
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DSI_VIDEO_MODE_FRAME_DONE);
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dsi_ctrl_enable_status_interrupt(dsi_ctrl,
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DSI_SINT_VIDEO_MODE_FRAME_DONE, NULL);
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reinit_completion(&dsi_ctrl->irq_info.vid_frame_done);
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ret = wait_for_completion_timeout(
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&dsi_ctrl->irq_info.vid_frame_done,
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msecs_to_jiffies(DSI_CTRL_TX_TO_MS));
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if (ret <= 0)
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DSI_CTRL_DEBUG(dsi_ctrl, "wait for video done failed\n");
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dsi_ctrl_disable_status_interrupt(dsi_ctrl,
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DSI_SINT_VIDEO_MODE_FRAME_DONE);
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timing = &(dsi_ctrl->host_config.video_timing);
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v_total = timing->v_sync_width + timing->v_back_porch +
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timing->v_front_porch + timing->v_active;
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v_blank = timing->v_sync_width + timing->v_back_porch;
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fps = timing->refresh_rate;
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sleep_ms = CEIL((v_blank * 1000), (v_total * fps)) + 1;
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udelay(sleep_ms * 1000);
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}
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int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl,
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u32 cmd_len,
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u32 *flags)
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@@ -1497,8 +1435,6 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl,
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}
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if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER)) {
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dsi_ctrl_wait_for_video_done(dsi_ctrl);
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atomic_set(&dsi_ctrl->dma_irq_trig, 0);
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dsi_ctrl_enable_status_interrupt(dsi_ctrl,
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DSI_SINT_CMD_MODE_DMA_DONE, NULL);
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@@ -3613,7 +3549,6 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags)
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if ((flags & DSI_CTRL_CMD_BROADCAST) &&
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(flags & DSI_CTRL_CMD_BROADCAST_MASTER)) {
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dsi_ctrl_wait_for_video_done(dsi_ctrl);
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atomic_set(&dsi_ctrl->dma_irq_trig, 0);
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dsi_ctrl_enable_status_interrupt(dsi_ctrl,
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DSI_SINT_CMD_MODE_DMA_DONE, NULL);
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@@ -3969,8 +3904,7 @@ int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl,
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* playback, display does not recover back after ESD failure.
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* Perform a reset if video engine is stuck.
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*/
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if (!on && (dsi_ctrl->version < DSI_CTRL_VERSION_1_3 ||
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vid_eng_busy))
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if (!on && vid_eng_busy)
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dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
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}
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@@ -31,9 +31,6 @@
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/**
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* enum dsi_ctrl_version - version of the dsi host controller
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* @DSI_CTRL_VERSION_UNKNOWN: Unknown controller version
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* @DSI_CTRL_VERSION_1_3: DSI host v1.3 controller
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* @DSI_CTRL_VERSION_1_4: DSI host v1.4 controller
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* @DSI_CTRL_VERSION_2_0: DSI host v2.0 controller
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* @DSI_CTRL_VERSION_2_2: DSI host v2.2 controller
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* @DSI_CTRL_VERSION_2_3: DSI host v2.3 controller
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* @DSI_CTRL_VERSION_2_4: DSI host v2.4 controller
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@@ -43,9 +40,6 @@
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*/
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enum dsi_ctrl_version {
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DSI_CTRL_VERSION_UNKNOWN,
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DSI_CTRL_VERSION_1_3,
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DSI_CTRL_VERSION_1_4,
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DSI_CTRL_VERSION_2_0,
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DSI_CTRL_VERSION_2_2,
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DSI_CTRL_VERSION_2_3,
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DSI_CTRL_VERSION_2_4,
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@@ -1,475 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "dsi_ctrl_hw.h"
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#include "dsi_ctrl_reg.h"
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#include "dsi_hw.h"
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#define MMSS_MISC_CLAMP_REG_OFF 0x0014
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/**
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* dsi_ctrl_hw_14_setup_lane_map() - setup mapping between
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* logical and physical lanes
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* @ctrl: Pointer to the controller host hardware.
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* @lane_map: Structure defining the mapping between DSI logical
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* lanes and physical lanes.
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*/
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void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl,
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struct dsi_lane_map *lane_map)
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{
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DSI_W32(ctrl, DSI_LANE_SWAP_CTRL, lane_map->lane_map_v1);
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DSI_CTRL_HW_DBG(ctrl, "Lane swap setup complete\n");
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}
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/**
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* dsi_ctrl_hw_14_wait_for_lane_idle()
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* This function waits for all the active DSI lanes to be idle by polling all
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* the FIFO_EMPTY bits and polling he lane status to ensure that all the lanes
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* are in stop state. This function assumes that the bus clocks required to
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* access the registers are already turned on.
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*
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* @ctrl: Pointer to the controller host hardware.
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* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
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* to be stopped.
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*
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* return: Error code.
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*/
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int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes)
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{
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int rc = 0, val = 0;
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u32 stop_state_mask = 0, fifo_empty_mask = 0;
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u32 const sleep_us = 10;
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u32 const timeout_us = 100;
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if (lanes & DSI_DATA_LANE_0) {
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stop_state_mask |= BIT(0);
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fifo_empty_mask |= (BIT(12) | BIT(16));
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}
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if (lanes & DSI_DATA_LANE_1) {
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stop_state_mask |= BIT(1);
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fifo_empty_mask |= BIT(20);
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}
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if (lanes & DSI_DATA_LANE_2) {
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stop_state_mask |= BIT(2);
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fifo_empty_mask |= BIT(24);
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}
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if (lanes & DSI_DATA_LANE_3) {
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stop_state_mask |= BIT(3);
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fifo_empty_mask |= BIT(28);
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}
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DSI_CTRL_HW_DBG(ctrl, "polling for fifo empty, mask=0x%08x\n",
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fifo_empty_mask);
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rc = readl_poll_timeout(ctrl->base + DSI_FIFO_STATUS, val,
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(val & fifo_empty_mask), sleep_us, timeout_us);
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if (rc) {
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DSI_CTRL_HW_ERR(ctrl, "fifo not empty, FIFO_STATUS=0x%08x\n",
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val);
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goto error;
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}
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DSI_CTRL_HW_DBG(ctrl, "polling for lanes to be in stop state, mask=0x%08x\n",
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stop_state_mask);
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rc = readl_poll_timeout(ctrl->base + DSI_LANE_STATUS, val,
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(val & stop_state_mask), sleep_us, timeout_us);
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if (rc) {
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DSI_CTRL_HW_ERR(ctrl, "lanes not in stop state, LANE_STATUS=0x%08x\n",
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val);
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goto error;
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}
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error:
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return rc;
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}
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/**
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* ulps_request() - request ulps entry for specified lanes
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* @ctrl: Pointer to the controller host hardware.
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* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
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* to enter ULPS.
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*
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* Caller should check if lanes are in ULPS mode by calling
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* get_lanes_in_ulps() operation.
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*/
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void dsi_ctrl_hw_cmn_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes)
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{
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u32 reg = 0;
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reg = DSI_R32(ctrl, DSI_LANE_CTRL);
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if (lanes & DSI_CLOCK_LANE)
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reg |= BIT(4);
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if (lanes & DSI_DATA_LANE_0)
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reg |= BIT(0);
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if (lanes & DSI_DATA_LANE_1)
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reg |= BIT(1);
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if (lanes & DSI_DATA_LANE_2)
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reg |= BIT(2);
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if (lanes & DSI_DATA_LANE_3)
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reg |= BIT(3);
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/*
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* ULPS entry request. Wait for short time to make sure
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* that the lanes enter ULPS. Recommended as per HPG.
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*/
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DSI_W32(ctrl, DSI_LANE_CTRL, reg);
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usleep_range(100, 110);
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DSI_CTRL_HW_DBG(ctrl, "ULPS requested for lanes 0x%x\n", lanes);
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}
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/**
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* ulps_exit() - exit ULPS on specified lanes
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* @ctrl: Pointer to the controller host hardware.
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* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
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* to exit ULPS.
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*
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* Caller should check if lanes are in active mode by calling
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* get_lanes_in_ulps() operation.
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*/
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void dsi_ctrl_hw_cmn_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
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{
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u32 reg = 0;
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u32 prev_reg = 0;
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prev_reg = DSI_R32(ctrl, DSI_LANE_CTRL);
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prev_reg &= BIT(24);
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if (lanes & DSI_CLOCK_LANE)
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reg |= BIT(12);
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if (lanes & DSI_DATA_LANE_0)
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reg |= BIT(8);
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if (lanes & DSI_DATA_LANE_1)
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reg |= BIT(9);
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if (lanes & DSI_DATA_LANE_2)
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reg |= BIT(10);
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if (lanes & DSI_DATA_LANE_3)
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reg |= BIT(11);
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/*
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* ULPS Exit Request
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* Hardware requirement is to wait for at least 1ms
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*/
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DSI_W32(ctrl, DSI_LANE_CTRL, reg | prev_reg);
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usleep_range(1000, 1010);
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/*
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* Sometimes when exiting ULPS, it is possible that some DSI
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* lanes are not in the stop state which could lead to DSI
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* commands not going through. To avoid this, force the lanes
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* to be in stop state.
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*/
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DSI_W32(ctrl, DSI_LANE_CTRL, (reg << 8) | prev_reg);
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wmb(); /* ensure lanes are put to stop state */
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DSI_W32(ctrl, DSI_LANE_CTRL, 0x0 | prev_reg);
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wmb(); /* ensure lanes are put to stop state */
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DSI_CTRL_HW_DBG(ctrl, "ULPS exit request for lanes=0x%x\n", lanes);
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}
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/**
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* get_lanes_in_ulps() - returns the list of lanes in ULPS mode
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* @ctrl: Pointer to the controller host hardware.
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*
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* Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
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* state. If 0 is returned, all the lanes are active.
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*
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* Return: List of lanes in ULPS state.
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*/
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u32 dsi_ctrl_hw_cmn_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl)
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{
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u32 reg = 0;
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u32 lanes = 0;
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|
||||
reg = DSI_R32(ctrl, DSI_LANE_STATUS);
|
||||
if (!(reg & BIT(8)))
|
||||
lanes |= DSI_DATA_LANE_0;
|
||||
if (!(reg & BIT(9)))
|
||||
lanes |= DSI_DATA_LANE_1;
|
||||
if (!(reg & BIT(10)))
|
||||
lanes |= DSI_DATA_LANE_2;
|
||||
if (!(reg & BIT(11)))
|
||||
lanes |= DSI_DATA_LANE_3;
|
||||
if (!(reg & BIT(12)))
|
||||
lanes |= DSI_CLOCK_LANE;
|
||||
|
||||
DSI_CTRL_HW_DBG(ctrl, "lanes in ulps = 0x%x\n", lanes);
|
||||
return lanes;
|
||||
}
|
||||
|
||||
/**
|
||||
* clamp_enable() - enable DSI clamps to keep PHY driving a stable link
|
||||
* @ctrl: Pointer to the controller host hardware.
|
||||
* @lanes: ORed list of lanes which need to be clamped.
|
||||
* @enable_ulps: Boolean to specify if ULPS is enabled in DSI controller
|
||||
*/
|
||||
void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl,
|
||||
u32 lanes,
|
||||
bool enable_ulps)
|
||||
{
|
||||
u32 clamp_reg = 0;
|
||||
u32 bit_shift = 0;
|
||||
u32 reg = 0;
|
||||
|
||||
if (ctrl->index == 1)
|
||||
bit_shift = 16;
|
||||
|
||||
if (lanes & DSI_CLOCK_LANE) {
|
||||
clamp_reg |= BIT(9);
|
||||
if (enable_ulps)
|
||||
clamp_reg |= BIT(8);
|
||||
}
|
||||
|
||||
if (lanes & DSI_DATA_LANE_0) {
|
||||
clamp_reg |= BIT(7);
|
||||
if (enable_ulps)
|
||||
clamp_reg |= BIT(6);
|
||||
}
|
||||
|
||||
if (lanes & DSI_DATA_LANE_1) {
|
||||
clamp_reg |= BIT(5);
|
||||
if (enable_ulps)
|
||||
clamp_reg |= BIT(4);
|
||||
}
|
||||
|
||||
if (lanes & DSI_DATA_LANE_2) {
|
||||
clamp_reg |= BIT(3);
|
||||
if (enable_ulps)
|
||||
clamp_reg |= BIT(2);
|
||||
}
|
||||
|
||||
if (lanes & DSI_DATA_LANE_3) {
|
||||
clamp_reg |= BIT(1);
|
||||
if (enable_ulps)
|
||||
clamp_reg |= BIT(0);
|
||||
}
|
||||
|
||||
reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
|
||||
reg |= (clamp_reg << bit_shift);
|
||||
DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
|
||||
|
||||
reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
|
||||
reg |= (BIT(15) << bit_shift); /* Enable clamp */
|
||||
DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
|
||||
|
||||
DSI_CTRL_HW_DBG(ctrl, "Clamps enabled for lanes=0x%x\n", lanes);
|
||||
}
|
||||
|
||||
/**
|
||||
* clamp_disable() - disable DSI clamps
|
||||
* @ctrl: Pointer to the controller host hardware.
|
||||
* @lanes: ORed list of lanes which need to have clamps released.
|
||||
* @disable_ulps: Boolean to specify if ULPS is enabled in DSI controller
|
||||
*/
|
||||
void dsi_ctrl_hw_14_clamp_disable(struct dsi_ctrl_hw *ctrl,
|
||||
u32 lanes,
|
||||
bool disable_ulps)
|
||||
{
|
||||
u32 clamp_reg = 0;
|
||||
u32 bit_shift = 0;
|
||||
u32 reg = 0;
|
||||
|
||||
if (ctrl->index == 1)
|
||||
bit_shift = 16;
|
||||
|
||||
if (lanes & DSI_CLOCK_LANE) {
|
||||
clamp_reg |= BIT(9);
|
||||
if (disable_ulps)
|
||||
clamp_reg |= BIT(8);
|
||||
}
|
||||
|
||||
if (lanes & DSI_DATA_LANE_0) {
|
||||
clamp_reg |= BIT(7);
|
||||
if (disable_ulps)
|
||||
clamp_reg |= BIT(6);
|
||||
}
|
||||
|
||||
if (lanes & DSI_DATA_LANE_1) {
|
||||
clamp_reg |= BIT(5);
|
||||
if (disable_ulps)
|
||||
clamp_reg |= BIT(4);
|
||||
}
|
||||
|
||||
if (lanes & DSI_DATA_LANE_2) {
|
||||
clamp_reg |= BIT(3);
|
||||
if (disable_ulps)
|
||||
clamp_reg |= BIT(2);
|
||||
}
|
||||
|
||||
if (lanes & DSI_DATA_LANE_3) {
|
||||
clamp_reg |= BIT(1);
|
||||
if (disable_ulps)
|
||||
clamp_reg |= BIT(0);
|
||||
}
|
||||
|
||||
clamp_reg |= BIT(15); /* Enable clamp */
|
||||
clamp_reg <<= bit_shift;
|
||||
|
||||
reg = DSI_MMSS_MISC_R32(ctrl, MMSS_MISC_CLAMP_REG_OFF);
|
||||
reg &= ~(clamp_reg);
|
||||
DSI_MMSS_MISC_W32(ctrl, MMSS_MISC_CLAMP_REG_OFF, reg);
|
||||
|
||||
DSI_CTRL_HW_DBG(ctrl, "Disable clamps for lanes=%d\n", lanes);
|
||||
}
|
||||
|
||||
#define DUMP_REG_VALUE(off) "\t%-30s: 0x%08x\n", #off, DSI_R32(ctrl, off)
|
||||
ssize_t dsi_ctrl_hw_14_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
|
||||
char *buf,
|
||||
u32 size)
|
||||
{
|
||||
u32 len = 0;
|
||||
|
||||
len += snprintf((buf + len), (size - len), "CONFIGURATION REGS:\n");
|
||||
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_HW_VERSION));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_FIFO_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_SYNC_DATATYPE));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_PIXEL_DATATYPE));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_BLANKING_DATATYPE));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_DATA_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_H));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_V));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_TOTAL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_HSYNC));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC_VPOS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_DMA_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DMA_CMD_OFFSET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DMA_CMD_LENGTH));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DMA_FIFO_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DMA_NULL_PACKET_DATA));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_TOTAL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_TOTAL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_ACK_ERR_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA0));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA1));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA2));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA3));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATATYPE0));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATATYPE1));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TRIG_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_EXT_MUX));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_EXT_MUX_TE_PULSE_DETECT_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CMD_MODE_DMA_SW_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CMD_MODE_MDP_SW_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CMD_MODE_BTA_SW_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RESET_SW_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_LANE_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_LANE_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_LANE_SWAP_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DLN0_PHY_ERR));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_LP_TIMER_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_HS_TIMER_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TIMEOUT_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CLKOUT_TIMING_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_EOT_PACKET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_EOT_PACKET_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_GENERIC_ESC_TX_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_ERR_INT_MASK0));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_INT_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_SOFT_RESET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CLK_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CLK_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_PHY_SW_RESET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_AXI2AHB_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL2));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_TOTAL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VBIF_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_AES_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL2));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_WRITE_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DSI_TIMING_FLUSH));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DSI_TIMING_DB_MODE));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_RESET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VERSION));
|
||||
|
||||
DSI_CTRL_HW_ERR(ctrl, "LLENGTH = %d\n", len);
|
||||
return len;
|
||||
}
|
||||
@@ -1,224 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
#include "dsi_ctrl_hw.h"
|
||||
#include "dsi_ctrl_reg.h"
|
||||
#include "dsi_hw.h"
|
||||
|
||||
void dsi_ctrl_hw_20_setup_lane_map(struct dsi_ctrl_hw *ctrl,
|
||||
struct dsi_lane_map *lane_map)
|
||||
{
|
||||
u32 reg_value = lane_map->lane_map_v2[DSI_LOGICAL_LANE_0] |
|
||||
(lane_map->lane_map_v2[DSI_LOGICAL_LANE_1] << 4) |
|
||||
(lane_map->lane_map_v2[DSI_LOGICAL_LANE_2] << 8) |
|
||||
(lane_map->lane_map_v2[DSI_LOGICAL_LANE_3] << 12);
|
||||
|
||||
DSI_W32(ctrl, DSI_LANE_SWAP_CTRL, reg_value);
|
||||
|
||||
DSI_CTRL_HW_DBG(ctrl, "Lane swap setup complete\n");
|
||||
}
|
||||
|
||||
int dsi_ctrl_hw_20_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl,
|
||||
u32 lanes)
|
||||
{
|
||||
int rc = 0, val = 0;
|
||||
u32 fifo_empty_mask = 0;
|
||||
u32 const sleep_us = 10;
|
||||
u32 const timeout_us = 100;
|
||||
|
||||
if (lanes & DSI_DATA_LANE_0)
|
||||
fifo_empty_mask |= (BIT(12) | BIT(16));
|
||||
|
||||
if (lanes & DSI_DATA_LANE_1)
|
||||
fifo_empty_mask |= BIT(20);
|
||||
|
||||
if (lanes & DSI_DATA_LANE_2)
|
||||
fifo_empty_mask |= BIT(24);
|
||||
|
||||
if (lanes & DSI_DATA_LANE_3)
|
||||
fifo_empty_mask |= BIT(28);
|
||||
|
||||
DSI_CTRL_HW_DBG(ctrl, "polling for fifo empty, mask=0x%08x\n",
|
||||
fifo_empty_mask);
|
||||
rc = readl_poll_timeout(ctrl->base + DSI_FIFO_STATUS, val,
|
||||
(val & fifo_empty_mask), sleep_us, timeout_us);
|
||||
if (rc) {
|
||||
DSI_CTRL_HW_ERR(ctrl, "fifo not empty, FIFO_STATUS=0x%08x\n",
|
||||
val);
|
||||
goto error;
|
||||
}
|
||||
|
||||
error:
|
||||
return rc;
|
||||
}
|
||||
|
||||
#define DUMP_REG_VALUE(off) "\t%-30s: 0x%08x\n", #off, DSI_R32(ctrl, off)
|
||||
ssize_t dsi_ctrl_hw_20_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
|
||||
char *buf,
|
||||
u32 size)
|
||||
{
|
||||
u32 len = 0;
|
||||
|
||||
len += snprintf((buf + len), (size - len), "CONFIGURATION REGS:\n");
|
||||
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_HW_VERSION));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_FIFO_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_SYNC_DATATYPE));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_PIXEL_DATATYPE));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_BLANKING_DATATYPE));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_DATA_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_H));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_ACTIVE_V));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_TOTAL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_HSYNC));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VIDEO_MODE_VSYNC_VPOS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_DMA_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DMA_CMD_OFFSET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DMA_CMD_LENGTH));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DMA_FIFO_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DMA_NULL_PACKET_DATA));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM0_TOTAL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM1_TOTAL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_ACK_ERR_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA0));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA1));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA2));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA3));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATATYPE0));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATATYPE1));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TRIG_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_EXT_MUX));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_EXT_MUX_TE_PULSE_DETECT_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CMD_MODE_DMA_SW_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CMD_MODE_MDP_SW_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CMD_MODE_BTA_SW_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RESET_SW_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_MISR_CMD_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_MISR_VIDEO_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_LANE_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_LANE_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_LANE_SWAP_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DLN0_PHY_ERR));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_LP_TIMER_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_HS_TIMER_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TIMEOUT_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CLKOUT_TIMING_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_EOT_PACKET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_EOT_PACKET_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_GENERIC_ESC_TX_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_ERR_INT_MASK0));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_INT_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_SOFT_RESET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CLK_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_CLK_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_PHY_SW_RESET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_AXI2AHB_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_MISR_CMD_MDP0_32BIT));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_MISR_CMD_MDP1_32BIT));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_MISR_VIDEO_32BIT));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_CTRL2));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_COMMAND_MODE_MDP_STREAM2_TOTAL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VBIF_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_AES_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_RDBK_DATA_CTRL));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TEST_PATTERN_GEN_CMD_DMA_INIT_VAL2));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_STATUS));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_WRITE_TRIGGER));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DSI_TIMING_FLUSH));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_DSI_TIMING_DB_MODE));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_TPG_DMA_FIFO_RESET));
|
||||
len += snprintf((buf + len), (size - len),
|
||||
DUMP_REG_VALUE(DSI_VERSION));
|
||||
|
||||
DSI_CTRL_HW_ERR(ctrl, "LLENGTH = %d\n", len);
|
||||
return len;
|
||||
}
|
||||
@@ -151,6 +151,120 @@ void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,
|
||||
DSI_CTRL_HW_DBG(ctrl, "Host configuration complete\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* ulps_request() - request ulps entry for specified lanes
|
||||
* @ctrl: Pointer to the controller host hardware.
|
||||
* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
|
||||
* to enter ULPS.
|
||||
*
|
||||
* Caller should check if lanes are in ULPS mode by calling
|
||||
* get_lanes_in_ulps() operation.
|
||||
*/
|
||||
void dsi_ctrl_hw_cmn_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes)
|
||||
{
|
||||
u32 reg = 0;
|
||||
|
||||
reg = DSI_R32(ctrl, DSI_LANE_CTRL);
|
||||
|
||||
if (lanes & DSI_CLOCK_LANE)
|
||||
reg |= BIT(4);
|
||||
if (lanes & DSI_DATA_LANE_0)
|
||||
reg |= BIT(0);
|
||||
if (lanes & DSI_DATA_LANE_1)
|
||||
reg |= BIT(1);
|
||||
if (lanes & DSI_DATA_LANE_2)
|
||||
reg |= BIT(2);
|
||||
if (lanes & DSI_DATA_LANE_3)
|
||||
reg |= BIT(3);
|
||||
|
||||
/*
|
||||
* ULPS entry request. Wait for short time to make sure
|
||||
* that the lanes enter ULPS. Recommended as per HPG.
|
||||
*/
|
||||
DSI_W32(ctrl, DSI_LANE_CTRL, reg);
|
||||
usleep_range(100, 110);
|
||||
|
||||
DSI_CTRL_HW_DBG(ctrl, "ULPS requested for lanes 0x%x\n", lanes);
|
||||
}
|
||||
|
||||
/**
|
||||
* ulps_exit() - exit ULPS on specified lanes
|
||||
* @ctrl: Pointer to the controller host hardware.
|
||||
* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
|
||||
* to exit ULPS.
|
||||
*
|
||||
* Caller should check if lanes are in active mode by calling
|
||||
* get_lanes_in_ulps() operation.
|
||||
*/
|
||||
void dsi_ctrl_hw_cmn_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes)
|
||||
{
|
||||
u32 reg = 0;
|
||||
u32 prev_reg = 0;
|
||||
|
||||
prev_reg = DSI_R32(ctrl, DSI_LANE_CTRL);
|
||||
prev_reg &= BIT(24);
|
||||
|
||||
if (lanes & DSI_CLOCK_LANE)
|
||||
reg |= BIT(12);
|
||||
if (lanes & DSI_DATA_LANE_0)
|
||||
reg |= BIT(8);
|
||||
if (lanes & DSI_DATA_LANE_1)
|
||||
reg |= BIT(9);
|
||||
if (lanes & DSI_DATA_LANE_2)
|
||||
reg |= BIT(10);
|
||||
if (lanes & DSI_DATA_LANE_3)
|
||||
reg |= BIT(11);
|
||||
|
||||
/*
|
||||
* ULPS Exit Request
|
||||
* Hardware requirement is to wait for at least 1ms
|
||||
*/
|
||||
DSI_W32(ctrl, DSI_LANE_CTRL, reg | prev_reg);
|
||||
usleep_range(1000, 1010);
|
||||
/*
|
||||
* Sometimes when exiting ULPS, it is possible that some DSI
|
||||
* lanes are not in the stop state which could lead to DSI
|
||||
* commands not going through. To avoid this, force the lanes
|
||||
* to be in stop state.
|
||||
*/
|
||||
DSI_W32(ctrl, DSI_LANE_CTRL, (reg << 8) | prev_reg);
|
||||
wmb(); /* ensure lanes are put to stop state */
|
||||
DSI_W32(ctrl, DSI_LANE_CTRL, 0x0 | prev_reg);
|
||||
wmb(); /* ensure lanes are put to stop state */
|
||||
|
||||
DSI_CTRL_HW_DBG(ctrl, "ULPS exit request for lanes=0x%x\n", lanes);
|
||||
}
|
||||
|
||||
/**
|
||||
* get_lanes_in_ulps() - returns the list of lanes in ULPS mode
|
||||
* @ctrl: Pointer to the controller host hardware.
|
||||
*
|
||||
* Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
|
||||
* state. If 0 is returned, all the lanes are active.
|
||||
*
|
||||
* Return: List of lanes in ULPS state.
|
||||
*/
|
||||
u32 dsi_ctrl_hw_cmn_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl)
|
||||
{
|
||||
u32 reg = 0;
|
||||
u32 lanes = 0;
|
||||
|
||||
reg = DSI_R32(ctrl, DSI_LANE_STATUS);
|
||||
if (!(reg & BIT(8)))
|
||||
lanes |= DSI_DATA_LANE_0;
|
||||
if (!(reg & BIT(9)))
|
||||
lanes |= DSI_DATA_LANE_1;
|
||||
if (!(reg & BIT(10)))
|
||||
lanes |= DSI_DATA_LANE_2;
|
||||
if (!(reg & BIT(11)))
|
||||
lanes |= DSI_DATA_LANE_3;
|
||||
if (!(reg & BIT(12)))
|
||||
lanes |= DSI_CLOCK_LANE;
|
||||
|
||||
DSI_CTRL_HW_DBG(ctrl, "lanes in ulps = 0x%x\n", lanes);
|
||||
return lanes;
|
||||
}
|
||||
|
||||
/**
|
||||
* phy_sw_reset() - perform a soft reset on the PHY.
|
||||
* @ctrl: Pointer to the controller host hardware.
|
||||
|
||||
Reference in New Issue
Block a user