disp: msm: sde: add dt based support for pm qos irq latency
This change adds dt based support for pm qos irq latency instead of using hardcoded value. Change-Id: I9f67ed1092eefac193a409773f841350532bc722 Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Dieser Commit ist enthalten in:
@@ -228,6 +228,7 @@ enum {
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PERF_CPU_MASK,
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PERF_CPU_MASK,
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CPU_MASK_PERF,
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CPU_MASK_PERF,
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PERF_CPU_DMA_LATENCY,
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PERF_CPU_DMA_LATENCY,
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PERF_CPU_IRQ_LATENCY,
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PERF_PROP_MAX,
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PERF_PROP_MAX,
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};
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};
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@@ -607,6 +608,8 @@ static struct sde_prop_type sde_perf_prop[] = {
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PROP_TYPE_U32},
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PROP_TYPE_U32},
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{PERF_CPU_DMA_LATENCY, "qcom,sde-qos-cpu-dma-latency", false,
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{PERF_CPU_DMA_LATENCY, "qcom,sde-qos-cpu-dma-latency", false,
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PROP_TYPE_U32},
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PROP_TYPE_U32},
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{PERF_CPU_IRQ_LATENCY, "qcom,sde-qos-cpu-irq-latency", false,
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PROP_TYPE_U32},
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};
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};
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static struct sde_prop_type sde_qos_prop[] = {
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static struct sde_prop_type sde_qos_prop[] = {
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@@ -4162,6 +4165,10 @@ static int _sde_perf_parse_dt_cfg(struct device_node *np,
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prop_exists[PERF_CPU_DMA_LATENCY] ?
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prop_exists[PERF_CPU_DMA_LATENCY] ?
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PROP_VALUE_ACCESS(prop_value, PERF_CPU_DMA_LATENCY, 0) :
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PROP_VALUE_ACCESS(prop_value, PERF_CPU_DMA_LATENCY, 0) :
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DEFAULT_CPU_DMA_LATENCY;
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DEFAULT_CPU_DMA_LATENCY;
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cfg->perf.cpu_irq_latency =
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prop_exists[PERF_CPU_IRQ_LATENCY] ?
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PROP_VALUE_ACCESS(prop_value, PERF_CPU_IRQ_LATENCY, 0) :
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PM_QOS_DEFAULT_VALUE;
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return 0;
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return 0;
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}
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}
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@@ -1317,6 +1317,7 @@ struct sde_sc_cfg {
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* @cpu_mask: pm_qos cpu mask value
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* @cpu_mask: pm_qos cpu mask value
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* @cpu_mask_perf: pm_qos cpu silver core mask value
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* @cpu_mask_perf: pm_qos cpu silver core mask value
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* @cpu_dma_latency: pm_qos cpu dma latency value
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* @cpu_dma_latency: pm_qos cpu dma latency value
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* @cpu_irq_latency: pm_qos cpu irq latency value
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* @axi_bus_width: axi bus width value in bytes
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* @axi_bus_width: axi bus width value in bytes
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* @num_mnoc_ports: number of mnoc ports
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* @num_mnoc_ports: number of mnoc ports
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*/
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*/
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@@ -1348,6 +1349,7 @@ struct sde_perf_cfg {
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unsigned long cpu_mask;
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unsigned long cpu_mask;
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unsigned long cpu_mask_perf;
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unsigned long cpu_mask_perf;
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u32 cpu_dma_latency;
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u32 cpu_dma_latency;
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u32 cpu_irq_latency;
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u32 axi_bus_width;
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u32 axi_bus_width;
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u32 num_mnoc_ports;
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u32 num_mnoc_ports;
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};
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};
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@@ -3008,6 +3008,7 @@ static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
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{
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{
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struct device *cpu_dev;
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struct device *cpu_dev;
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int cpu = 0;
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int cpu = 0;
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u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
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if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
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if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
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SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
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SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
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@@ -3024,12 +3025,12 @@ static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
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if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
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if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
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dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
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dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
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sde_kms->catalog->perf.cpu_dma_latency);
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cpu_irq_latency);
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else
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else
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dev_pm_qos_add_request(cpu_dev,
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dev_pm_qos_add_request(cpu_dev,
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&sde_kms->pm_qos_irq_req[cpu],
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&sde_kms->pm_qos_irq_req[cpu],
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DEV_PM_QOS_RESUME_LATENCY,
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DEV_PM_QOS_RESUME_LATENCY,
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sde_kms->catalog->perf.cpu_dma_latency);
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cpu_irq_latency);
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}
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}
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}
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}
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