qcacmn: Add support for HW cookie conversion

Support HW cookie conversion for BE platform. Change-Id: I39058fbf256266557f5e734ba376db4db0731b24 CRs-Fixed: 2929533
2021-02-22 03:22:07 -08:00
--- a/hal/wifi3.0/be/hal_be_api.h
+++ b/hal/wifi3.0/be/hal_be_api.h
@@ -22,6 +22,24 @@
 #include "hal_hw_headers.h"
 #include "hal_rx.h"

+struct hal_hw_cc_config {
+	uint32_t lut_base_addr_31_0;
+	uint32_t cc_global_en:1,
+		 page_4k_align:1,
+		 cookie_offset_msb:5,
+		 cookie_page_msb:5,
+		 lut_base_addr_39_32:8,
+		 wbm2sw6_cc_en:1,
+		 wbm2sw5_cc_en:1,
+		 wbm2sw4_cc_en:1,
+		 wbm2sw3_cc_en:1,
+		 wbm2sw2_cc_en:1,
+		 wbm2sw1_cc_en:1,
+		 wbm2sw0_cc_en:1,
+		 wbm2fw_cc_en:1,
+		 reserved:4;
+};
+
 #define HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr) \
 	((struct rx_msdu_ext_desc_info *) \
 	_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
@@ -104,4 +122,15 @@ void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl,
 			    qdf_dma_addr_t hw_qdesc_paddr,
 			    int pn_type);

+/**
+ * hal_cookie_conversion_reg_cfg_be() - set cookie conversion relevant register
+ *					for REO/WBM
+ * @soc: HAL soc handle
+ * @cc_cfg: structure pointer for HW cookie conversion configuration
+ *
+ * Return: None
+ */
+void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,
+				      struct hal_hw_cc_config *cc_cfg);
+
 #endif /* _HAL_BE_API_H_ */
--- a/hal/wifi3.0/be/hal_be_generic_api.c
+++ b/hal/wifi3.0/be/hal_be_generic_api.c
@@ -710,6 +710,113 @@ static uint8_t hal_rx_reo_buf_type_get_be(hal_ring_desc_t rx_desc)
 	return HAL_RX_REO_BUF_TYPE_GET(rx_desc);
 }

+#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
+#define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000
+#endif
+void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,
+				      struct hal_hw_cc_config *cc_cfg)
+{
+	uint32_t reg_addr, reg_val = 0;
+	struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
+
+	/* REO CFG */
+	reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE);
+	reg_val = cc_cfg->lut_base_addr_31_0;
+	HAL_REG_WRITE(soc, reg_addr, reg_val);
+
+	reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE);
+	reg_val = 0;
+	reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
+			  SW_COOKIE_CONVERT_GLOBAL_ENABLE,
+			  cc_cfg->cc_global_en);
+	reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
+			  SW_COOKIE_CONVERT_ENABLE,
+			  cc_cfg->cc_global_en);
+	reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
+			  PAGE_ALIGNMENT,
+			  cc_cfg->page_4k_align);
+	reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
+			  COOKIE_OFFSET_MSB,
+			  cc_cfg->cookie_offset_msb);
+	reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
+			  COOKIE_PAGE_MSB,
+			  cc_cfg->cookie_page_msb);
+	reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
+			  CMEM_LUT_BASE_ADDR_39_32,
+			  cc_cfg->lut_base_addr_39_32);
+	HAL_REG_WRITE(soc, reg_addr, reg_val);
+
+	/* WBM CFG */
+	reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE);
+	reg_val = cc_cfg->lut_base_addr_31_0;
+	HAL_REG_WRITE(soc, reg_addr, reg_val);
+
+	reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE);
+	reg_val = 0;
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
+			  PAGE_ALIGNMENT,
+			  cc_cfg->page_4k_align);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
+			  COOKIE_OFFSET_MSB,
+			  cc_cfg->cookie_offset_msb);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
+			  COOKIE_PAGE_MSB,
+			  cc_cfg->cookie_page_msb);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
+			  CMEM_LUT_BASE_ADDR_39_32,
+			  cc_cfg->lut_base_addr_39_32);
+	HAL_REG_WRITE(soc, reg_addr, reg_val);
+
+	/*
+	 * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE,
+	 */
+	reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE);
+	reg_val = 0;
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
+			  WBM_COOKIE_CONV_GLOBAL_ENABLE,
+			  cc_cfg->cc_global_en);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
+			  WBM2SW6_COOKIE_CONVERSION_EN,
+			  cc_cfg->wbm2sw6_cc_en);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
+			  WBM2SW5_COOKIE_CONVERSION_EN,
+			  cc_cfg->wbm2sw5_cc_en);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
+			  WBM2SW4_COOKIE_CONVERSION_EN,
+			  cc_cfg->wbm2sw4_cc_en);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
+			  WBM2SW3_COOKIE_CONVERSION_EN,
+			  cc_cfg->wbm2sw3_cc_en);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
+			  WBM2SW2_COOKIE_CONVERSION_EN,
+			  cc_cfg->wbm2sw2_cc_en);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
+			  WBM2SW1_COOKIE_CONVERSION_EN,
+			  cc_cfg->wbm2sw1_cc_en);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
+			  WBM2SW0_COOKIE_CONVERSION_EN,
+			  cc_cfg->wbm2sw0_cc_en);
+	reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
+			  WBM2FW_COOKIE_CONVERSION_EN,
+			  cc_cfg->wbm2fw_cc_en);
+	HAL_REG_WRITE(soc, reg_addr, reg_val);
+
+#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
+	/*
+	 * To enable indication for HW cookie conversion done or not for
+	 * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th
+	 * bit spare_control[15] should be set.
+	 */
+	reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE);
+	reg_val = HAL_REG_READ(soc, reg_addr);
+	reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL,
+			  SPARE_CONTROL,
+			  HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15);
+	HAL_REG_WRITE(soc, reg_addr, reg_val);
+#endif
+}
+qdf_export_symbol(hal_cookie_conversion_reg_cfg_be);
+
 /**
 * hal_hw_txrx_default_ops_attach_be() - Attach the default hal ops for
 *		beryllium chipsets.
--- a/hal/wifi3.0/be/hal_be_rx.h
+++ b/hal/wifi3.0/be/hal_be_rx.h
@@ -279,6 +279,41 @@ hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, uint64_t pa,
 	/* TODO */
 }

+#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
+/* HW set dowrd-2 bit16 to 1 if HW CC is done */
+#define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_OFFSET 0x8
+#define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_MASK 0x10000
+#define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_LSB 0x10
+/**
+ * hal_rx_wbm_get_cookie_convert_done() - Get cookie conversion done flag
+ * @hal_desc: wbm Rx ring descriptor pointer
+ *
+ * This function will get the bit value that indicate HW cookie
+ * conversion done or not
+ *
+ * Return: 1 - HW cookie conversion done, 0 - not
+ */
+static inline uint8_t hal_rx_wbm_get_cookie_convert_done(void *hal_desc)
+{
+	return HAL_RX_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_RX,
+			  CC_DONE);
+}
+#endif
+
+/**
+ * hal_rx_wbm_get_desc_va() - Get Desc virtual address within WBM Desc
+ * @hal_desc: RX WBM2SW ring descriptor pointer
+ *
+ * Return: RX descriptor virtual address
+ */
+static inline uint64_t hal_rx_wbm_get_desc_va(void *hal_desc)
+{
+	return HAL_RX_GET(hal_desc, WBM2SW_COMPLETION_RING_RX,
+			  BUFFER_VIRT_ADDR_31_0) |
+		(((uint64_t)HAL_RX_GET(hal_desc, WBM2SW_COMPLETION_RING_RX,
+			   BUFFER_VIRT_ADDR_63_32)) << 32);
+}
+
 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc)		\
 	(((*(((uint32_t *)wbm_desc) +			\
 	(WBM_RELEASE_RING_FIRST_MSDU_OFFSET >> 2))) & \
@@ -376,4 +411,18 @@ hal_rx_msdu_desc_info_get_be(void *desc_addr,
 	msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info);
 }

+/**
+ * hal_rx_get_reo_desc_va() - Get Desc virtual address within REO Desc
+ * @reo_desc: REO2SW ring descriptor pointer
+ *
+ * Return: RX descriptor virtual address
+ */
+static inline uint64_t hal_rx_get_reo_desc_va(void *reo_desc)
+{
+	return HAL_RX_GET(reo_desc, REO_DESTINATION_RING,
+			  BUFFER_VIRT_ADDR_31_0) |
+		(((uint64_t)HAL_RX_GET(reo_desc, REO_DESTINATION_RING,
+			   BUFFER_VIRT_ADDR_63_32)) << 32);
+}
+
 #endif /* _HAL_BE_RX_H_ */
--- a/hal/wifi3.0/be/hal_be_tx.h
+++ b/hal/wifi3.0/be/hal_be_tx.h
@@ -20,6 +20,7 @@
 #define _HAL_BE_TX_H_

 #include "hal_be_hw_headers.h"
+#include "hal_tx.h"

 enum hal_be_tx_ret_buf_manager {
 	HAL_BE_WBM_SW0_BM_ID = 5,
@@ -279,6 +280,45 @@ static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
 	return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32));
 }

+#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
+/* HW set dowrd-2 bit30 to 1 if HW CC is done */
+#define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_OFFSET 0x8
+#define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_MASK 0x40000000
+#define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_LSB 0x1E
+/**
+ * hal_tx_comp_get_cookie_convert_done() - Get cookie conversion done flag
+ * @hal_desc: completion ring descriptor pointer
+ *
+ * This function will get the bit value that indicate HW cookie
+ * conversion done or not
+ *
+ * Return: 1 - HW cookie conversion done, 0 - not
+ */
+static inline uint8_t hal_tx_comp_get_cookie_convert_done(void *hal_desc)
+{
+	return HAL_TX_DESC_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_TX,
+			       CC_DONE);
+}
+#endif
+
+/**
+ * hal_tx_comp_get_desc_va() - Get Desc virtual address within completion Desc
+ * @hal_desc: completion ring descriptor pointer
+ *
+ * This function will get the TX Desc virtual address
+ *
+ * Return: TX desc virtual address
+ */
+static inline uint64_t hal_tx_comp_get_desc_va(void *hal_desc)
+{
+	return HAL_TX_DESC_GET(hal_desc, WBM2SW_COMPLETION_RING_TX,
+				BUFFER_VIRT_ADDR_31_0) |
+		(((uint64_t)HAL_TX_DESC_GET(
+				hal_desc,
+				WBM2SW_COMPLETION_RING_TX,
+				BUFFER_VIRT_ADDR_63_32)) << 32);
+}
+
 /*---------------------------------------------------------------------------
 * TX BANK register accessor APIs
 * ---------------------------------------------------------------------------
--- a/hal/wifi3.0/hal_api.h
+++ b/hal/wifi3.0/hal_api.h
@@ -2833,4 +2833,21 @@ uint32_t hal_get_ring_usage(
 	ring_usage = (100 * num_valid) / srng->num_entries;
 	return ring_usage;
 }
+
+/**
+ * hal_cmem_write() - function for CMEM buffer writing
+ * @hal_soc_hdl: HAL SOC handle
+ * @offset: CMEM address
+ * @value: value to write
+ *
+ * Return: None.
+ */
+static inline void hal_cmem_write(hal_soc_handle_t hal_soc_hdl,
+				  uint32_t offset,
+				  uint32_t value)
+{
+	struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
+
+	hal_write32_mb(hal, offset, value);
+}
 #endif /* _HAL_APIH_ */