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@@ -23,7 +23,7 @@
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#define AON_MVP_NOC_RESET 0x0001F000
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#define AON_MVP_NOC_RESET 0x0001F000
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#define CPU_BASE_OFFS_IRIS33 0x000A0000
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#define CPU_BASE_OFFS_IRIS33 0x000A0000
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#define AON_BASE_OFFS 0x000E0000
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#define AON_BASE_OFFS 0x000E0000
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-#define VCODEC_VIDEO_CC_BASE 0x00F00000
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+#define VCODEC_VIDEO_CC_BASE 0x000F0000
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#define CPU_CS_BASE_OFFS_IRIS33 (CPU_BASE_OFFS_IRIS33)
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#define CPU_CS_BASE_OFFS_IRIS33 (CPU_BASE_OFFS_IRIS33)
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#define CPU_IC_BASE_OFFS_IRIS33 (CPU_BASE_OFFS_IRIS33)
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#define CPU_IC_BASE_OFFS_IRIS33 (CPU_BASE_OFFS_IRIS33)
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