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@@ -12185,6 +12185,166 @@ update_tx_ilp:
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}
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#endif
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+#ifdef WLAN_SUPPORT_DPDK
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+static char *tcl_ring_name[] = {
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+ "tcl_data_ring1",
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+ "tcl_data_ring2",
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+ "tcl_data_ring3",
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+ "tcl_data_ring4",
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+ "tcl_data_ring5",
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+};
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+
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+static char *tcl_comp_ring_name[] = {
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+ "tcl_comp_ring1",
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+ "tcl_comp_ring2",
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+ "tcl_comp_ring3",
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+ "tcl_comp_ring4",
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+ "tcl_comp_ring5",
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+};
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+
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+static char *reo_dest_ring_name[] = {
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+ "reo_dest_ring1",
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+ "reo_dest_ring2",
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+ "reo_dest_ring3",
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+ "reo_dest_ring4",
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+ "reo_dest_ring5",
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+ "reo_dest_ring6",
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+ "reo_dest_ring7",
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+ "reo_dest_ring8",
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+};
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+
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+static void dp_dpdk_get_ring_info(struct cdp_soc_t *soc_hdl,
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+ qdf_uio_info_t *uio_info)
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+{
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+ struct dp_soc *soc = (struct dp_soc *)soc_hdl;
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+ struct hal_soc *hal_soc = (struct hal_soc *)soc->hal_soc;
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+ struct hal_srng *hal_srng;
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+ uint8_t idx = 1, i;
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+
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+ /* WBM Desc Release Ring */
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+ hal_srng = (struct hal_srng *)
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+ soc->tcl_data_ring[0].hal_srng;
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+
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+ hal_srng = (struct hal_srng *)
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+ soc->wbm_desc_rel_ring.hal_srng;
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+ uio_info->mem[idx].name = "wbm_desc_rel_ring";
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+ uio_info->mem[idx].addr = (unsigned long)hal_srng->ring_base_paddr;
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+ uio_info->mem[idx].size =
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+ (hal_srng->num_entries * hal_srng->entry_size) << 2;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+
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+ /* WBM Idle Link Ring */
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+ hal_srng = (struct hal_srng *)
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+ soc->wbm_idle_link_ring.hal_srng;
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+ uio_info->mem[idx].name = "wbm_idle_link_ring";
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+ uio_info->mem[idx].addr = (unsigned long)hal_srng->ring_base_paddr;
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+ uio_info->mem[idx].size =
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+ (hal_srng->num_entries * hal_srng->entry_size) << 2;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+
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+ /* TCL Data Rings */
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+ for (i = 0; i < soc->num_tcl_data_rings; i++) {
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+ hal_srng = (struct hal_srng *)
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+ soc->tcl_data_ring[i].hal_srng;
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+ uio_info->mem[idx].name = tcl_ring_name[i];
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+ uio_info->mem[idx].addr =
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+ (unsigned long)hal_srng->ring_base_paddr;
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+ uio_info->mem[idx].size =
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+ (hal_srng->num_entries * hal_srng->entry_size) << 2;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+ }
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+
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+ /* TCL Completion Rings */
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+ for (i = 0; i < soc->num_tcl_data_rings; i++) {
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+ hal_srng = (struct hal_srng *)
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+ soc->tx_comp_ring[i].hal_srng;
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+ uio_info->mem[idx].name = tcl_comp_ring_name[i];
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+ uio_info->mem[idx].addr =
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+ (unsigned long)hal_srng->ring_base_paddr;
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+ uio_info->mem[idx].size =
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+ (hal_srng->num_entries * hal_srng->entry_size) << 2;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+ }
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+
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+ /* Reo Dest Rings */
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+ for (i = 0; i < soc->num_reo_dest_rings; i++) {
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+ hal_srng = (struct hal_srng *)
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+ soc->reo_dest_ring[i].hal_srng;
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+ uio_info->mem[idx].name = reo_dest_ring_name[i];
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+ uio_info->mem[idx].addr =
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+ (unsigned long)hal_srng->ring_base_paddr;
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+ uio_info->mem[idx].size =
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+ (hal_srng->num_entries * hal_srng->entry_size) << 2;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+ }
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+
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+ /* RXDMA Refill Ring */
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+ hal_srng = (struct hal_srng *)
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+ soc->rx_refill_buf_ring[0].hal_srng;
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+ uio_info->mem[idx].name = "rxdma_buf_ring";
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+ uio_info->mem[idx].addr = (unsigned long)hal_srng->ring_base_paddr;
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+ uio_info->mem[idx].size =
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+ (hal_srng->num_entries * hal_srng->entry_size) << 2;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+
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+ /* REO Exception Ring */
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+ hal_srng = (struct hal_srng *)
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+ soc->reo_exception_ring.hal_srng;
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+ uio_info->mem[idx].name = "reo_exception_ring";
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+ uio_info->mem[idx].addr =
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+ (unsigned long)hal_srng->ring_base_paddr;
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+ uio_info->mem[idx].size =
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+ (hal_srng->num_entries * hal_srng->entry_size) << 2;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+
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+ /* RX Release Ring */
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+ hal_srng = (struct hal_srng *)
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+ soc->rx_rel_ring.hal_srng;
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+ uio_info->mem[idx].name = "rx_release_ring";
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+ uio_info->mem[idx].addr = (unsigned long)hal_srng->ring_base_paddr;
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+ uio_info->mem[idx].size =
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+ (hal_srng->num_entries * hal_srng->entry_size) << 2;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+
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+ /* Reo Reinject Ring */
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+ hal_srng = (struct hal_srng *)
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+ soc->reo_reinject_ring.hal_srng;
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+ uio_info->mem[idx].name = "reo_reinject_ring";
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+ uio_info->mem[idx].addr =
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+ (unsigned long)hal_srng->ring_base_paddr;
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+ uio_info->mem[idx].size =
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+ (hal_srng->num_entries * hal_srng->entry_size) << 2;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+
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+ /* Shadow Write Pointer for LMAC Ring */
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+ uio_info->mem[idx].name = "lmac_shadow_wrptr";
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+ uio_info->mem[idx].addr =
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+ (unsigned long)hal_soc->shadow_wrptr_mem_paddr;
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+ uio_info->mem[idx].size =
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+ sizeof(*(hal_soc->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+ idx++;
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+
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+ /* Shadow Write Pointer for LMAC Ring */
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+ uio_info->mem[idx].name = "lmac_shadow_rdptr";
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+ uio_info->mem[idx].addr =
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+ (unsigned long)hal_soc->shadow_rdptr_mem_paddr;
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+ uio_info->mem[idx].size =
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+ sizeof(*(hal_soc->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX;
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+ uio_info->mem[idx].memtype = UIO_MEM_PHYS;
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+
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+}
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+#endif
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+
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static struct cdp_cmn_ops dp_ops_cmn = {
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.txrx_soc_attach_target = dp_soc_attach_target_wifi3,
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.txrx_vdev_attach = dp_vdev_attach_wifi3,
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@@ -12321,6 +12481,9 @@ static struct cdp_cmn_ops dp_ops_cmn = {
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#ifdef WLAN_SUPPORT_RX_FISA
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.get_fst_cmem_base = dp_rx_fisa_get_cmem_base,
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#endif
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+#ifdef WLAN_SUPPORT_DPDK
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+ .dpdk_get_ring_info = dp_dpdk_get_ring_info,
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+#endif
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};
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static struct cdp_ctrl_ops dp_ops_ctrl = {
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@@ -14375,6 +14538,10 @@ static QDF_STATUS dp_pdev_init(struct cdp_soc_t *txrx_soc,
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dp_soc_reset_intr_mask(soc);
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}
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+ /* Reset the ring interrupt mask if DPDK is enabled */
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+ if (wlan_cfg_get_dp_soc_dpdk_cfg(soc->ctrl_psoc)) {
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+ dp_soc_reset_dpdk_intr_mask(soc);
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+ }
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/* Reset the cpu ring map if radio is NSS offloaded */
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dp_soc_reset_ipa_vlan_intr_mask(soc);
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