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@@ -0,0 +1,372 @@
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+/*
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+ * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
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+ *
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+ * Permission to use, copy, modify, and/or distribute this software for
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+ * any purpose with or without fee is hereby granted, provided that the
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+ * above copyright notice and this permission notice appear in all
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+ * copies.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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+ * PERFORMANCE OF THIS SOFTWARE.
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+ */
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+
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+/**
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+ * DOC: if_ahb_reset.c
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+ *
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+ * c file for ahb ipq4019 specific implementations.
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+ */
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+
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+#include "hif.h"
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+#include "hif_main.h"
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+#include "hif_debug.h"
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+#include "hif_io32.h"
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+#include "ce_main.h"
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+#include "ce_tasklet.h"
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+#include "ahb_api.h"
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+#include "if_ahb.h"
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+
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+#include <linux/clk.h>
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+#include <linux/reset.h>
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+#include <linux/of_address.h>
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+#include <linux/platform_device.h>
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+#include <linux/device.h>
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+#include <linux/of.h>
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+
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+/**
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+ * clk_enable_disable() - Enable/disable clock
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+ * @dev : pointer to device structure
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+ * @str : clock name
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+ * @enable : should be true, if the clock needs to be enabled
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+ * should be false, if the clock needs to be enabled
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+ *
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+ * This is a helper function for hif_ahb_clk_enable_disable to enable
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+ * disable clocks.
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+ * clk_prepare_enable will enable the clock
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+ * clk_disable_unprepare will disable the clock
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+ *
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+ * Return: zero on success, non-zero incase of error.
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+ */
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+
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+static int clk_enable_disable(struct device *dev, const char *str, int enable)
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+{
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+ struct clk *clk_t = NULL;
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+ int ret;
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+
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+ clk_t = clk_get(dev, str);
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+ if (IS_ERR(clk_t)) {
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+ HIF_INFO("%s: Failed to get %s clk %ld\n",
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+ __func__, str, PTR_ERR(clk_t));
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+ return -EFAULT;
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+ }
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+ if (TRUE == enable) {
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+ /* Prepare and Enable clk */
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+ ret = clk_prepare_enable(clk_t);
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+ if (ret) {
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+ HIF_INFO("%s: err enabling clk %s , error:%d\n",
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+ __func__, str, ret);
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+ return ret;
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+ }
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+ } else {
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+ /* Disable and unprepare clk */
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+ clk_disable_unprepare(clk_t);
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+ }
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+ return 0;
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+}
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+
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+
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+/**
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+ * hif_ahb_clk_enable_disable() - Enable/disable ahb clock
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+ * @dev : pointer to device structure
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+ * @enable : should be true, if the clock needs to be enabled
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+ * should be false, if the clock needs to be enabled
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+ *
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+ * This functions helps to enable/disable all the necesasary clocks
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+ * for bus access.
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+ *
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+ * Return: zero on success, non-zero incase of error
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+ */
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+int hif_ahb_clk_enable_disable(struct device *dev, int enable)
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+{
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+ int ret;
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+
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+ ret = clk_enable_disable(dev, "wifi_wcss_cmd", enable);
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+ if (ret)
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+ return ret;
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+ ret = clk_enable_disable(dev, "wifi_wcss_ref", enable);
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+ if (ret)
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+ return ret;
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+ ret = clk_enable_disable(dev, "wifi_wcss_rtc", enable);
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+ if (ret)
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+ return ret;
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+ return 0;
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+}
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+
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+/**
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+ * hif_enable_radio() - Enable the target radio.
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+ * @sc : pointer to the hif context
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+ *
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+ * This function helps to release the target from reset state
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+ *
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+ * Return : zero on success, non-zero incase of error.
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+ */
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+int hif_ahb_enable_radio(struct hif_pci_softc *sc,
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+ struct platform_device *pdev,
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+ const struct platform_device_id *id)
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+{
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+ struct reset_control *reset_ctl = NULL;
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+ uint32_t msi_addr, msi_base, wifi_core_id;
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+ struct hif_softc *scn = HIF_GET_SOFTC(sc);
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+ struct device_node *dev_node = pdev->dev.of_node;
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+ bool msienable = false;
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+ int ret = 0;
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+
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+ ret = of_property_read_u32(dev_node, "qca,msi_addr", &msi_addr);
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+ if (ret) {
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+ HIF_INFO("%s: Unable to get msi_addr - error:%d\n",
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+ __func__, ret);
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+ return -EIO;
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+ }
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+ ret = of_property_read_u32(dev_node, "qca,msi_base", &msi_base);
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+ if (ret) {
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+ HIF_INFO("%s: Unable to get msi_base - error:%d\n",
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+ __func__, ret);
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+ return -EIO;
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+ }
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+ ret = of_property_read_u32(dev_node, "core-id", &wifi_core_id);
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+ if (ret) {
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+ HIF_INFO("%s: Unable to get core-id - error:%d\n",
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+ __func__, ret);
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+ return -EIO;
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+ }
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+
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+ /* Program the above values into Wifi scratch regists */
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+ if (msienable) {
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+ hif_write32_mb(sc->mem + FW_AXI_MSI_ADDR, msi_addr);
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+ hif_write32_mb(sc->mem + FW_AXI_MSI_DATA, msi_base);
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+ }
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+
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+ /* TBD: Temporary changes. Frequency should be
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+ retrieved through clk_xxx once kernel GCC driver is available */
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+ {
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+ void __iomem *mem_gcc;
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+ uint32_t clk_sel;
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+ uint32_t gcc_fepll_pll_div;
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+ uint32_t wifi_cpu_freq[4] = {266700000, 250000000, 222200000,
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+ 200000000};
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+ uint32_t current_freq = 0;
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+
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+ /* Enable WIFI clock input */
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+ if (scn->target_info.target_type == TARGET_TYPE_IPQ4019) {
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+ ret = hif_ahb_clk_enable_disable(&pdev->dev, 1);
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+ if (ret) {
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+ HIF_INFO("%s:Error while enabling clock :%d\n",
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+ __func__, ret);
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+ return ret;
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+ }
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+ }
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+
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+ mem_gcc = ioremap_nocache(GCC_BASE, GCC_SIZE);
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+ if (IS_ERR(mem_gcc)) {
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+ HIF_INFO("%s: GCC ioremap failed\n", __func__);
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+ return PTR_ERR(mem_gcc);
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+ }
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+ gcc_fepll_pll_div = hif_read32_mb(mem_gcc + GCC_FEPLL_PLL_DIV);
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+ clk_sel = (wifi_core_id == 0) ? ((gcc_fepll_pll_div &
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+ GCC_FEPLL_PLL_CLK_WIFI_0_SEL_MASK) >>
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+ GCC_FEPLL_PLL_CLK_WIFI_0_SEL_SHIFT) :
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+ ((gcc_fepll_pll_div & GCC_FEPLL_PLL_CLK_WIFI_1_SEL_MASK)
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+ >> GCC_FEPLL_PLL_CLK_WIFI_1_SEL_SHIFT);
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+ current_freq = wifi_cpu_freq[clk_sel];
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+
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+ HIF_INFO("Wifi%d CPU frequency %u\n", wifi_core_id,
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+ current_freq);
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+ hif_write32_mb(sc->mem + FW_CPU_PLL_CONFIG, gcc_fepll_pll_div);
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+ iounmap(mem_gcc);
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+ }
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+
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+ /* De-assert radio cold reset */
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+ reset_ctl = reset_control_get(&pdev->dev, "wifi_radio_cold");
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+ if (IS_ERR(reset_ctl)) {
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+ HIF_INFO("%s: Failed to get radio cold reset control\n",
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+ __func__);
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+ ret = PTR_ERR(reset_ctl);
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+ goto err_reset;
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+ }
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+ reset_control_deassert(reset_ctl);
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+ reset_control_put(reset_ctl);
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+
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+ /* De-assert radio warm reset */
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+ reset_ctl = reset_control_get(&pdev->dev, "wifi_radio_warm");
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+ if (IS_ERR(reset_ctl)) {
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+ HIF_INFO("%s: Failed to get radio warm reset control\n",
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+ __func__);
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+ ret = PTR_ERR(reset_ctl);
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+ goto err_reset;
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+ }
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+ reset_control_deassert(reset_ctl);
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+ reset_control_put(reset_ctl);
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+
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+ /* De-assert radio srif reset */
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+ reset_ctl = reset_control_get(&pdev->dev, "wifi_radio_srif");
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+ if (IS_ERR(reset_ctl)) {
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+ HIF_INFO("%s: Failed to get radio srif reset control\n",
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+ __func__);
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+ ret = PTR_ERR(reset_ctl);
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+ goto err_reset;
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+ }
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+ reset_control_deassert(reset_ctl);
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+ reset_control_put(reset_ctl);
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+
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+ /* De-assert target CPU reset */
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+ reset_ctl = reset_control_get(&pdev->dev, "wifi_cpu_init");
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+ if (IS_ERR(reset_ctl)) {
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+ HIF_INFO("%s: Failed to get cpu init reset control", __func__);
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+ ret = PTR_ERR(reset_ctl);
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+ goto err_reset;
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+ }
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+ reset_control_deassert(reset_ctl);
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+ reset_control_put(reset_ctl);
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+
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+ return 0;
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+
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+err_reset:
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+ return -EIO;
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+
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+}
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+
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+/* "wifi_core_warm" is the other reset type */
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+#define AHB_RESET_TYPE "wifi_core_cold"
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+
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+/**
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+ * hif_ahb_device_reset() - Disable the radio and held the radio is reset state.
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+ * @scn : pointer to the hif context
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+ *
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+ * This function will hold the target in reset state.
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+ * Will be called while unload the driver or any graceful unload path.
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+ *
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+ * Return : n/a.
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+ */
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+void hif_ahb_device_reset(struct hif_softc *scn)
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+{
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+ struct reset_control *resetctl = NULL;
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+ struct reset_control *core_resetctl = NULL;
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+ struct hif_pci_softc *sc = HIF_GET_PCI_SOFTC(scn);
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+ struct platform_device *pdev = (struct platform_device *)(sc->pdev);
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+ uint32_t glb_cfg_offset;
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+ uint32_t haltreq_offset;
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+ uint32_t haltack_offset;
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+ void __iomem *mem_tcsr;
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+ uint32_t wifi_core_id;
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+ uint32_t reg_value;
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+ int wait_limit = ATH_AHB_RESET_WAIT_MAX;
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+
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+
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+ wifi_core_id = hif_read32_mb(sc->mem + WLAN_SUBSYSTEM_CORE_ID_ADDRESS);
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+ glb_cfg_offset = (wifi_core_id == 0) ? TCSR_WIFI0_GLB_CFG :
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+ TCSR_WIFI1_GLB_CFG;
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+ haltreq_offset = (wifi_core_id == 0) ? TCSR_WCSS0_HALTREQ :
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+ TCSR_WCSS1_HALTREQ;
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+ haltack_offset = (wifi_core_id == 0) ? TCSR_WCSS0_HALTACK :
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+ TCSR_WCSS1_HALTACK;
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+
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+ mem_tcsr = ioremap_nocache(TCSR_BASE, TCSR_SIZE);
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+ if (IS_ERR(mem_tcsr)) {
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+ HIF_INFO("%s: TCSR ioremap failed\n", __func__);
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+ return;
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+ }
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+ reg_value = hif_read32_mb(mem_tcsr + haltreq_offset);
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+ hif_write32_mb(mem_tcsr + haltreq_offset, reg_value | 0x1);
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+ /* Wait for halt ack before asserting reset */
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+ while (wait_limit) {
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+
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+ if (hif_read32_mb(mem_tcsr + haltack_offset) & 0x1)
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+ break;
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+
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+ A_MDELAY(1);
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+ wait_limit--;
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+ }
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+
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+ reg_value = hif_read32_mb(mem_tcsr + glb_cfg_offset);
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+ hif_write32_mb(mem_tcsr + glb_cfg_offset, reg_value | (1 << 25));
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+
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+ core_resetctl = reset_control_get(&pdev->dev, AHB_RESET_TYPE);
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+ if (IS_ERR(core_resetctl)) {
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+ HIF_INFO("Failed to get wifi core cold reset control\n");
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+ return;
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+ }
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+
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+ /* Reset wifi core */
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+ reset_control_assert(core_resetctl);
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+
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+ /* TBD: Check if we should also assert other bits (radio_cold, radio_
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+ warm, radio_srif, cpu_ini) */
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+ A_MDELAY(1); /* TBD: Get reqd delay from HW team */
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+
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+ /* Assert radio cold reset */
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+ resetctl = reset_control_get(&pdev->dev, "wifi_radio_cold");
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+ if (IS_ERR(resetctl)) {
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+ HIF_INFO("%s: Failed to get radio cold reset control\n",
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+ __func__);
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+ return;
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+ }
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+ reset_control_assert(resetctl);
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+ A_MDELAY(1); /* TBD: Get reqd delay from HW team */
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+ reset_control_put(resetctl);
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+
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+ /* Assert radio warm reset */
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+ resetctl = reset_control_get(&pdev->dev, "wifi_radio_warm");
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+ if (IS_ERR(resetctl)) {
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+ HIF_INFO("%s: Failed to get radio warm reset control\n",
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+ __func__);
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+ return;
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+ }
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+ reset_control_assert(resetctl);
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+ A_MDELAY(1); /* TBD: Get reqd delay from HW team */
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+ reset_control_put(resetctl);
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+
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+ /* Assert radio srif reset */
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+ resetctl = reset_control_get(&pdev->dev, "wifi_radio_srif");
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+ if (IS_ERR(resetctl)) {
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+ HIF_INFO("%s: Failed to get radio srif reset control\n",
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+ __func__);
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+ return;
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+ }
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+ reset_control_assert(resetctl);
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+ A_MDELAY(1); /* TBD: Get reqd delay from HW team */
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+ reset_control_put(resetctl);
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+
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+ /* Assert target CPU reset */
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+ resetctl = reset_control_get(&pdev->dev, "wifi_cpu_init");
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+ if (IS_ERR(resetctl)) {
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+ HIF_INFO("%s: Failed to get cpu init reset control", __func__);
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+ return;
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+ }
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+ reset_control_assert(resetctl);
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+ A_MDELAY(10); /* TBD: Get reqd delay from HW team */
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+ reset_control_put(resetctl);
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+
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+ /* Clear gbl_cfg and haltreq before clearing Wifi core reset */
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+ reg_value = hif_read32_mb(mem_tcsr + haltreq_offset);
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+ hif_write32_mb(mem_tcsr + haltreq_offset, reg_value & ~0x1);
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+ reg_value = hif_read32_mb(mem_tcsr + glb_cfg_offset);
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+ hif_write32_mb(mem_tcsr + glb_cfg_offset, reg_value & ~(1 << 25));
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+
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+ /* de-assert wifi core reset */
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+ reset_control_deassert(core_resetctl);
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+
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+ A_MDELAY(1); /* TBD: Get reqd delay from HW team */
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+
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+ /* TBD: Check if we should de-assert other bits here */
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+ reset_control_put(core_resetctl);
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+ iounmap(mem_tcsr);
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+ HIF_INFO("Reset complete for wifi core id : %d\n", wifi_core_id);
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+}
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+
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+
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+
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Houston Hoffman