Merge "msm: camera: cpas: Change to set OT value to 8 for RT block" into camera-kernel.lnx.5.0

drivers/cam_cpas/cpas_top/cpastop_v165_100.h

@@ -298,6 +298,27 @@ static struct cam_camnoc_specific
 			.offset = 0x3620, /* IFE01234_RDI_MAXWR_LOW */
 			.value = 0x0,
 		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4808, /* IFE01234_RDI_QOSGEN_MAINCTL */
+			.value = 0x2,
+		},
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4820, /* IFE01234_RDI_QOSGEN_SHAPING_LOW */
+			.value = 0x07070707,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4824, /* IFE01234_RDI_QOSGEN_SHAPING_HIGH */
+			.value = 0x07070707,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE01_NRDI_WRITE,
@@ -360,6 +381,27 @@ static struct cam_camnoc_specific
 			.offset = 0x3A20, /* IFE01_MAXWR_LOW */
 			.value = 0x0,
 		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4708, /* IFE01_NRDI_QOSGEN_MAINCTL */
+			.value = 0x2,
+		},
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4720, /* IFE01_NRDI_QOSGEN_SHAPING_LOW */
+			.value = 0x07070707,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4724, /* IFE01_NRDI_QOSGEN_SHAPING_HIGH */
+			.value = 0x07070707,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE2_NRDI_WRITE,
@@ -422,6 +464,27 @@ static struct cam_camnoc_specific
 			.offset = 0x5420, /* IFE2_MAXWR_LOW */
 			.value = 0x0,
 		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5188, /* IFE2_NRDI_QOSGEN_MAINCTL */
+			.value = 0x2,
+		},
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x51A0, /* IFE2_NRDI_QOSGEN_SHAPING_LOW */
+			.value = 0x07070707,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x51A4, /* IFE2_NRDI_QOSGEN_SHAPING_HIGH */
+			.value = 0x07070707,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,