qcacmn: Increse num TX rings for QCN9224

This change includes below
1) Changes needed to increase Tx rings to 4
2) Use WBM2SW4 ring for rx error in QCN9224
3) memset srng at alloc to avoid populating RBM_id
in per packet path and enable implicit RBM

Change-Id: Icbd5ac2378273b8f3c6adc41c611e29551fff22f
This commit is contained in:
Chaithanya Garrepalli
2021-10-09 14:47:58 +05:30
committed by Madan Koyyalamudi
parent de13832745
commit 3c3e5709ac
15 changed files with 148 additions and 23 deletions

View File

@@ -602,6 +602,35 @@ hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl,
*
* Return: void
*/
#ifdef DP_TX_IMPLICIT_RBM_MAPPING
static inline void
hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
dma_addr_t paddr, uint8_t rbm_id,
uint32_t desc_id, uint8_t type)
{
/* Set buffer_addr_info.buffer_addr_31_0 */
HAL_SET_FLD(desc, TCL_DATA_CMD,
BUF_ADDR_INFO_BUFFER_ADDR_31_0) =
HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr);
/* Set buffer_addr_info.buffer_addr_39_32 */
HAL_SET_FLD(desc, TCL_DATA_CMD,
BUF_ADDR_INFO_BUFFER_ADDR_39_32) |=
HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32,
(((uint64_t)paddr) >> 32));
/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
HAL_SET_FLD(desc, TCL_DATA_CMD,
BUF_ADDR_INFO_SW_BUFFER_COOKIE) |=
HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE,
desc_id);
/* Set Buffer or Ext Descriptor Type */
HAL_SET_FLD(desc, TCL_DATA_CMD,
BUF_OR_EXT_DESC_TYPE) |=
HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type);
}
#else
static inline void
hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
dma_addr_t paddr, uint8_t rbm_id,
@@ -635,6 +664,7 @@ hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
BUF_OR_EXT_DESC_TYPE) |=
HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type);
}
#endif
#ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT

View File

@@ -253,6 +253,8 @@ enum hal_rx_mpdu_desc_flags {
#define HAL_RX_BUF_RBM_SW5_BM(sw0_bm_id) (sw0_bm_id + 5)
#define HAL_RX_BUF_RBM_SW6_BM(sw0_bm_id) (sw0_bm_id + 6)
#define HAL_RX_BUF_RBM_SW_BM(sw0_bm_id, wbm2sw_id) (sw0_bm_id + wbm2sw_id)
#define HAL_REO_DESTINATION_RING_MSDU_COUNT_OFFSET 0x8
#define HAL_REO_DESTINATION_RING_MSDU_COUNT_LSB 0
#define HAL_REO_DESTINATION_RING_MSDU_COUNT_MASK 0x000000ff