Merge changes I841105b4,I4a971058,I4697bb54 into camera-kernel.lnx.7.0

* changes:
  msm: camera: isp: Correct sync mode of HW in Dual TFE usecase
  msm: camera: isp: Fix crash if PPI hw is not present
  cam: tfe: Correct master select and halt mode

drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c

@@ -1251,6 +1251,9 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl(
 				out_port->secure_mode == 1))
 				continue;
 
+			csid_acquire.sync_mode = ((i == CAM_ISP_HW_SPLIT_LEFT) ?
+				CAM_ISP_HW_SYNC_MASTER : CAM_ISP_HW_SYNC_SLAVE);
+
 			hw_intf = csid_res_iterator->hw_res[i]->hw_intf;
 			csid_acquire.master_idx = hw_intf->hw_idx;
 

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid770.h

@@ -51,7 +51,7 @@ static struct cam_tfe_csid_pxl_reg_offset  cam_tfe_csid_770_ipp_reg_offset = {
 	.early_eof_en_shift_val              = 29,
 	.halt_master_sel_shift               = 4,
 	.halt_mode_shift                     = 2,
-	.halt_master_sel_master_val          = 3,
+	.halt_master_sel_master_val          = 1,
 	.halt_master_sel_slave_val           = 0,
 	.binning_supported                   = 3,
 	.bin_qcfa_en_shift_val               = 30,
@@ -104,7 +104,7 @@ static struct cam_tfe_csid_pxl_reg_offset  cam_tfe_csid_770_ppp_reg_offset = {
 	.halt_master_sel_shift               = 4,
 	.halt_mode_shift                     = 2,
 	.halt_master_sel_master_val          = 3,
-	.halt_master_sel_slave_val           = 0,
+	.halt_master_sel_slave_val           = 2,
 	.binning_supported                   = 0,
 	.bin_qcfa_en_shift_val               = 30,
 	.bin_en_shift_val                    = 2,
@@ -273,7 +273,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset
 	.csid_csi2_rx_stats_ecc_addr                  = 0x164,
 	.csid_csi2_rx_total_crc_err_addr              = 0x168,
 
-	.phy_tpg_base_id                              = 0,
+	.phy_tpg_base_id                              = 3,
 	.csi2_rst_srb_all                             = 0x3FFF,
 	.csi2_rst_done_shift_val                      = 27,
 	.csi2_irq_mask_all                            = 0xFFFFFFF,
@@ -290,6 +290,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset
 	.csi2_rx_long_pkt_hdr_rst_stb_shift           = 0x1,
 	.csi2_rx_short_pkt_hdr_rst_stb_shift          = 0x2,
 	.csi2_rx_cphy_pkt_hdr_rst_stb_shift           = 0x3,
+	.need_to_sel_tpg_mux                          = true,
 };
 
 static struct cam_tfe_csid_common_reg_offset

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c

@@ -821,9 +821,11 @@ static int cam_tfe_csid_cid_reserve(struct cam_tfe_csid_hw *csid_hw,
 	}
 
 	csid_hw->csi2_reserve_cnt++;
-	CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired reserv cnt:%d",
+	CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired reserv cnt:%d phy_sel: %d res_id: %d",
 		csid_hw->hw_intf->hw_idx, *cid_value,
-		csid_hw->csi2_reserve_cnt);
+		csid_hw->csi2_reserve_cnt,
+		csid_hw->csi2_rx_cfg.phy_sel,
+		cid_reserv->in_port->res_id);
 
 end:
 	return rc;
@@ -1134,7 +1136,7 @@ static int cam_tfe_csid_enable_csi2(
 	 */
 	ppi_index = csid_hw->csi2_rx_cfg.phy_sel - csid_reg->csi2_reg->phy_sel_base;
 
-	if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) {
+	if (csid_hw->ppi_enable && csid_hw->ppi_hw_intf[ppi_index]) {
 		ppi_lane_cfg.lane_type = csid_hw->csi2_rx_cfg.lane_type;
 		ppi_lane_cfg.lane_num  = csid_hw->csi2_rx_cfg.lane_num;
 		ppi_lane_cfg.lane_cfg  = csid_hw->csi2_rx_cfg.lane_cfg;
@@ -1178,7 +1180,7 @@ static int cam_tfe_csid_disable_csi2(
 		csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr);
 
 	ppi_index = csid_hw->csi2_rx_cfg.phy_sel - csid_reg->csi2_reg->phy_sel_base;
-	if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) {
+	if (csid_hw->ppi_enable && csid_hw->ppi_hw_intf[ppi_index]) {
 		/* De-Initialize the PPI bridge */
 		CAM_DBG(CAM_ISP, "ppi_index to de-init %d\n", ppi_index);
 		rc = csid_hw->ppi_hw_intf[ppi_index]->hw_ops.deinit(
@@ -1652,7 +1654,7 @@ static int cam_tfe_csid_enable_pxl_path(
 		val = (TFE_CSID_HALT_MODE_SLAVE << pxl_reg->halt_mode_shift);
 	else
 		/* Default is internal halt mode */
-		val = 0;
+		val = 1 << pxl_reg->halt_master_sel_shift;
 
 	/*
 	 * Resume at frame boundary if Master or No Sync.
@@ -1866,7 +1868,17 @@ static int cam_tfe_csid_enable_ppp_path(
 			ppp_reg->halt_master_sel_shift);
 	else
 		/* Default is internal halt mode */
-		val = 0;
+		val = (TFE_CSID_HALT_MODE_SLAVE  << ppp_reg->halt_mode_shift) |
+			(ppp_reg->halt_master_sel_master_val <<
+			ppp_reg->halt_master_sel_shift);
+
+	/*
+	 * Resume at frame boundary if Master or No Sync.
+	 * Slave will get resume command from Master.
+	 */
+	if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER ||
+		path_data->sync_mode == CAM_ISP_HW_SYNC_NONE)
+		val |= CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY;
 
 	cam_io_w_mb(val, soc_info->reg_map[0].mem_base + ppp_reg->csid_pxl_ctrl_addr);