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msm: sde: Uprev IGC version to 4.0 to indicate existence of LUT 257

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Change IGC version to 4.0 to clearly indicate that support
for LUT 257 in DSPP is now supported and expected.

Change-Id: Ie3bb5b0150bdf6c332f86d0ae416b4f6fc42e70f
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
This commit is contained in:
Christopher Braga
2020-03-24 16:06:11 -04:00
committed by Gopikrishnaiah Anandan
parent 077c72680b
commit 394f727493
4 changed files with 8 additions and 7 deletions
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1
msm/sde/sde_color_processing.c
View File

@@ -2757,6 +2757,7 @@ static void dspp_igc_install_property(struct drm_crtc *crtc)
"SDE_DSPP_IGC_V", version);
switch (version) {
case 3:
case 4:
sde_cp_crtc_install_blob_property(crtc, feature_name,
SDE_CP_CRTC_DSPP_IGC, sizeof(struct drm_msm_igc_lut));
break;

4
msm/sde/sde_hw_dspp.c
View File

@@ -49,11 +49,11 @@ static void dspp_igc(struct sde_hw_dspp *c)
else
c->ops.setup_igc = sde_setup_dspp_igcv3;
} else if (c->cap->sblk->igc.version ==
SDE_COLOR_PROCESS_VER(0x3, 0x2)) {
SDE_COLOR_PROCESS_VER(0x4, 0x0)) {
c->ops.setup_igc = NULL;
ret = reg_dmav2_init_dspp_op_v4(SDE_DSPP_IGC, c->idx);
if (!ret)
c->ops.setup_igc = reg_dmav2_setup_dspp_igcv32;
c->ops.setup_igc = reg_dmav2_setup_dspp_igcv4;
}
}

6
msm/sde/sde_hw_reg_dma_v1_color_proc.c
View File

@@ -3995,7 +3995,7 @@ static void _perform_sbdma_kickoff(struct sde_hw_dspp *ctx,
}
}
static void _dspp_igcv32_off(struct sde_hw_dspp *ctx, void *cfg)
static void _dspp_igcv4_off(struct sde_hw_dspp *ctx, void *cfg)
{
struct sde_hw_cp_cfg *hw_cfg = cfg;
struct sde_hw_reg_dma_ops *dma_ops;
@@ -4036,7 +4036,7 @@ static void _dspp_igcv32_off(struct sde_hw_dspp *ctx, void *cfg)
_perform_sbdma_kickoff(ctx, hw_cfg, dma_ops, blk, IGC);
}
void reg_dmav2_setup_dspp_igcv32(struct sde_hw_dspp *ctx, void *cfg)
void reg_dmav2_setup_dspp_igcv4(struct sde_hw_dspp *ctx, void *cfg)
{
struct drm_msm_igc_lut *lut_cfg;
struct sde_hw_reg_dma_ops *dma_ops;
@@ -4052,7 +4052,7 @@ void reg_dmav2_setup_dspp_igcv32(struct sde_hw_dspp *ctx, void *cfg)
if (!hw_cfg->payload) {
DRM_DEBUG_DRIVER("disable igc feature\n");
_dspp_igcv32_off(ctx, cfg);
_dspp_igcv4_off(ctx, cfg);
return;
}

4
msm/sde/sde_hw_reg_dma_v1_color_proc.h
View File

@@ -275,11 +275,11 @@ int reg_dmav1_deinit_ltm_ops(enum sde_dspp idx);
int reg_dmav2_init_dspp_op_v4(int feature, enum sde_dspp idx);
/**
* reg_dmav2_setup_dspp_igcv32() - igc v32 implementation using reg dma v2.
* reg_dmav2_setup_dspp_igcv4() - igc v4 implementation using reg dma v2.
* @ctx: dspp ctx info
* @cfg: pointer to struct sde_hw_cp_cfg
*/
void reg_dmav2_setup_dspp_igcv32(struct sde_hw_dspp *ctx, void *cfg);
void reg_dmav2_setup_dspp_igcv4(struct sde_hw_dspp *ctx, void *cfg);
/**
* reg_dmav2_setup_3d_gamutv43() - gamut v4_3 implementation using reg dma v2.