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@@ -75,6 +75,7 @@ do { \
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#define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
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#define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4)
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#define HAL_TX_BITS_PER_TID 3
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+#define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1)
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#define HAL_TX_NUM_DSCP_PER_REGISTER 10
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#define HAL_MAX_HW_DSCP_TID_MAPS 2
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@@ -1033,6 +1034,7 @@ static inline void hal_tx_update_dscp_tid(void *hal_soc, uint8_t tid,
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int index;
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uint32_t addr;
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uint32_t value;
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+ uint32_t regval;
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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@@ -1049,8 +1051,15 @@ static inline void hal_tx_update_dscp_tid(void *hal_soc, uint8_t tid,
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addr += 4 * (dscp/HAL_TX_NUM_DSCP_PER_REGISTER);
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value = tid << (HAL_TX_BITS_PER_TID * index);
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+ /* Read back previous DSCP TID config and update
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+ * with new config.
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+ */
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+ regval = HAL_REG_READ(soc, addr);
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+ regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
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+ regval |= value;
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+
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HAL_REG_WRITE(soc, addr,
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- (value & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK));
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+ (regval & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK));
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}
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/**
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