qcacmn: Add hal_tx_desc_set_mesh_en API

Implement hal_tx_desc_set_mesh_en API
based on the chipset as
the macro to set mesh_en value is
chipset dependent.

Change-Id: I43c85e4ed6fd4f9992de5b71857cdb8becd1dd36
CRs-Fixed: 2522133

dp/wifi3.0/dp_tx.c

@@ -1133,7 +1133,7 @@ static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
 		hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
 
 	if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
-		hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
+		hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
 
 
 	tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_get());

hal/wifi3.0/hal_internal.h

@@ -349,6 +349,7 @@ struct hal_hw_txrx_ops {
 	void (*hal_tx_comp_get_status)(void *desc, void *ts,
 				       struct hal_soc *hal);
 	uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc);
+	void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en);
 
 	/* rx */
 	uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);

hal/wifi3.0/hal_tx.h

@@ -425,6 +425,7 @@ static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
 
 /**
  * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor
+ * @hal_soc_hdl: hal soc handle
  * @desc: Handle to Tx Descriptor
  * @en:   For raw WiFi frames, this indicates transmission to a mesh STA,
  *        enabling the interpretation of the 'Mesh Control Present' bit
@@ -434,10 +435,12 @@ static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
  *
  * Return: void
  */
-static inline void hal_tx_desc_set_mesh_en(void *desc, uint8_t en)
+static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl,
+					   void *desc, uint8_t en)
 {
-	HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
-		HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
+
+	hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en);
 }
 
 /**

hal/wifi3.0/qca6290/hal_6290.c

@@ -740,6 +740,24 @@ hal_rx_msdu_end_sa_sw_peer_id_get_6290(uint8_t *buf)
 
 	return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
 }
+
+/**
+ * hal_tx_desc_set_mesh_en_6290 - Set mesh_enable flag in Tx descriptor
+ * @desc: Handle to Tx Descriptor
+ * @en:   For raw WiFi frames, this indicates transmission to a mesh STA,
+ *        enabling the interpretation of the 'Mesh Control Present' bit
+ *        (bit 8) of QoS Control (otherwise this bit is ignored),
+ *        For native WiFi frames, this indicates that a 'Mesh Control' field
+ *        is present between the header and the LLC.
+ *
+ * Return: void
+ */
+static inline
+void hal_tx_desc_set_mesh_en_6290(void *desc, uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
+		HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
+}
 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
 	/* init and setup */
 	hal_srng_dst_hw_init_generic,
@@ -759,7 +777,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
 	hal_tx_desc_set_cache_set_num_generic,
 	hal_tx_comp_get_status_generic,
 	hal_tx_comp_get_release_reason_generic,
-
+	hal_tx_desc_set_mesh_en_6290,
 	/* rx */
 	hal_rx_msdu_start_nss_get_6290,
 	hal_rx_mon_hw_desc_get_mpdu_status_6290,

hal/wifi3.0/qca6390/hal_6390.c

@@ -739,6 +739,24 @@ hal_rx_msdu_end_sa_sw_peer_id_get_6390(uint8_t *buf)
 	return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
 }
 
+/**
+ * hal_tx_desc_set_mesh_en_6390 - Set mesh_enable flag in Tx descriptor
+ * @desc: Handle to Tx Descriptor
+ * @en:   For raw WiFi frames, this indicates transmission to a mesh STA,
+ *        enabling the interpretation of the 'Mesh Control Present' bit
+ *        (bit 8) of QoS Control (otherwise this bit is ignored),
+ *        For native WiFi frames, this indicates that a 'Mesh Control' field
+ *        is present between the header and the LLC.
+ *
+ * Return: void
+ */
+static inline
+void hal_tx_desc_set_mesh_en_6390(void *desc, uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
+		HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
+}
+
 struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
 	/* init and setup */
 	hal_srng_dst_hw_init_generic,
@@ -758,7 +776,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
 	hal_tx_desc_set_cache_set_num_generic,
 	hal_tx_comp_get_status_generic,
 	hal_tx_comp_get_release_reason_generic,
-
+	hal_tx_desc_set_mesh_en_6390,
 	/* rx */
 	hal_rx_msdu_start_nss_get_6390,
 	hal_rx_mon_hw_desc_get_mpdu_status_6390,

hal/wifi3.0/qca6490/hal_6490.c

@@ -611,7 +611,27 @@ static void hal_reo_status_get_header_6490(uint32_t *d, int b, void *h1)
 		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
 }
 
+/**
+ * hal_tx_desc_set_mesh_en_6490 - Set mesh_enable flag in Tx descriptor
+ * @desc: Handle to Tx Descriptor
+ * @en:   For raw WiFi frames, this indicates transmission to a mesh STA,
+ *        enabling the interpretation of the 'Mesh Control Present' bit
+ *        (bit 8) of QoS Control (otherwise this bit is ignored),
+ *        For native WiFi frames, this indicates that a 'Mesh Control' field
+ *        is present between the header and the LLC.
+ *
+ * Return: void
+ */
+static inline
+void hal_tx_desc_set_mesh_en_6490(void *desc, uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |=
+		HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
+}
+
 struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
+	/* tx */
+	hal_tx_desc_set_mesh_en_6490,
 	/* rx */
 	hal_rx_get_rx_fragment_number_6490,
 	hal_rx_msdu_end_da_is_mcbc_get_6490,

hal/wifi3.0/qca8074v1/hal_8074v1.c

@@ -737,6 +737,24 @@ hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf)
 	return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
 }
 
+/**
+ * hal_tx_desc_set_mesh_en_8074v1 - Set mesh_enable flag in Tx descriptor
+ * @desc: Handle to Tx Descriptor
+ * @en:   For raw WiFi frames, this indicates transmission to a mesh STA,
+ *        enabling the interpretation of the 'Mesh Control Present' bit
+ *        (bit 8) of QoS Control (otherwise this bit is ignored),
+ *        For native WiFi frames, this indicates that a 'Mesh Control' field
+ *        is present between the header and the LLC.
+ *
+ * Return: void
+ */
+static inline
+void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
+		HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
+}
+
 struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
 
 	/* init and setup */
@@ -757,7 +775,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
 	hal_tx_desc_set_cache_set_num_generic,
 	hal_tx_comp_get_status_generic,
 	hal_tx_comp_get_release_reason_generic,
-
+	hal_tx_desc_set_mesh_en_8074v1,
 	/* rx */
 	hal_rx_msdu_start_nss_get_8074,
 	hal_rx_mon_hw_desc_get_mpdu_status_8074,

hal/wifi3.0/qca8074v2/hal_8074v2.c

@@ -734,6 +734,24 @@ hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf)
 	return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
 }
 
+/**
+ * hal_tx_desc_set_mesh_en_8074v2 - Set mesh_enable flag in Tx descriptor
+ * @desc: Handle to Tx Descriptor
+ * @en:   For raw WiFi frames, this indicates transmission to a mesh STA,
+ *        enabling the interpretation of the 'Mesh Control Present' bit
+ *        (bit 8) of QoS Control (otherwise this bit is ignored),
+ *        For native WiFi frames, this indicates that a 'Mesh Control' field
+ *        is present between the header and the LLC.
+ *
+ * Return: void
+ */
+static inline
+void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
+		HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
+}
+
 struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
 
 	/* init and setup */
@@ -754,6 +772,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
 	hal_tx_desc_set_cache_set_num_generic,
 	hal_tx_comp_get_status_generic,
 	hal_tx_comp_get_release_reason_generic,
+	hal_tx_desc_set_mesh_en_8074v2,
 
 	/* rx */
 	hal_rx_msdu_start_nss_get_8074v2,

hal/wifi3.0/qcn9000/hal_9000.c

@@ -743,6 +743,24 @@ hal_rx_msdu_end_sa_sw_peer_id_get_9000(uint8_t *buf)
 	return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
 }
 
+/**
+ * hal_tx_desc_set_mesh_en_9000 - Set mesh_enable flag in Tx descriptor
+ * @desc: Handle to Tx Descriptor
+ * @en:   For raw WiFi frames, this indicates transmission to a mesh STA,
+ *        enabling the interpretation of the 'Mesh Control Present' bit
+ *        (bit 8) of QoS Control (otherwise this bit is ignored),
+ *        For native WiFi frames, this indicates that a 'Mesh Control' field
+ *        is present between the header and the LLC.
+ *
+ * Return: void
+ */
+static inline
+void hal_tx_desc_set_mesh_en_9000(void *desc, uint8_t en)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
+		HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
+}
+
 struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
 
 	/* init and setup */
@@ -763,6 +781,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
 	hal_tx_desc_set_cache_set_num_generic,
 	hal_tx_comp_get_status_generic,
 	hal_tx_comp_get_release_reason_generic,
+	hal_tx_desc_set_mesh_en_9000,
 
 	/* rx */
 	hal_rx_msdu_start_nss_get_8074v2,