video: driver: enc fix to run sample HEVC NV12C testcase

Allocate ARP buffer in CB4 to avoid HW hang issue.
Add support to set HFI_PROP_RAW_RESOLUTION at enc INPUT port
and did necessary changes to set HFI_PROP_CROP_OFFSETS at
OUTPUT port only for encoder. Also added support to set
missing basic control properties to video firmware.

Change-Id: If5bc2940d37ac20c1889cd4de466be09f1e1f28b
Signed-off-by: Akshata Sahukar <asahukar@codeaurora.org>
This commit is contained in:
Akshata Sahukar
2020-12-15 15:57:19 -08:00
parent a2f47ddf00
commit 38b9dd655f
10 changed files with 346 additions and 92 deletions

View File

@@ -70,8 +70,8 @@ enum hfi_color_format {
#define HFI_BITMASK_BITSTREAM_HEIGHT 0x0000ffff
#define HFI_PROP_BITSTREAM_RESOLUTION 0x03000103
#define HFI_BITMASK_LINEAR_STRIDE 0xffff0000
#define HFI_BITMASK_LINEAR_SCANLINE 0x0000ffff
#define HFI_BITMASK_LINEAR_STRIDE 0xffff0000
#define HFI_BITMASK_LINEAR_SCANLINE 0x0000ffff
#define HFI_PROP_LINEAR_STRIDE_SCANLINE 0x03000104
#define HFI_BITMASK_CROP_RIGHT_OFFSET 0xffff0000
@@ -245,7 +245,7 @@ enum hfi_rate_control {
#define HFI_PROP_CONTENT_ADAPTIVE_CODING 0x0300012c
#define HFI_PROP_CONST_QUALITY_BITRATE_BOOST 0x0300012d
#define HFI_PROP_BITRATE_BOOST 0x0300012d
#define HFI_BITMASK_QP_I 0x000000ff
#define HFI_BITMASK_QP_P 0x0000ff00
@@ -305,6 +305,11 @@ enum hfi_layer_encoding_type {
#define HFI_PROP_HEIC_GRID_ENABLE 0x03000144
enum hfi_syncframe_request_mode {
HFI_SYNC_FRAME_REQUEST_WITHOUT_SEQ_HDR = 0x00000001,
HFI_SYNC_FRAME_REQUEST_WITH_PREFIX_SEQ_HDR = 0x00000002,
};
#define HFI_PROP_REQUEST_SYNC_FRAME 0x03000145
#define HFI_PROP_MAX_GOP_FRAMES 0x03000146
@@ -316,7 +321,6 @@ enum hfi_quality_mode {
HFI_MODE_POWER_SAVE = 0x2,
};
// TODO (AS): Does not map to any V4l2 control
#define HFI_PROP_QUALITY_MODE 0x03000148
enum hfi_seq_header_mode {
@@ -454,6 +458,19 @@ enum hfi_picture_type {
#define HFI_PROP_ROI_INFO 0x03000173
#define HFI_PROP_WORST_COMPRESSION_RATIO 0x03000174
#define HFI_PROP_WORST_COMPLEXITY_FACTOR 0x03000175
//TODO: Enable when firmware adds support for these
//#define HFI_PROP_VBV_DELAY 0x03000176
//#define HFI_PROP_SEQ_CHANGE_AT_SYNC_FRAME 0x03000177
#define HFI_BITMASK_RAW_WIDTH 0xffff0000
#define HFI_BITMASK_RAW_HEIGHT 0x0000ffff
#define HFI_PROP_RAW_RESOLUTION 0x03000178
#define HFI_PROP_END 0x03FFFFFF
#define HFI_SESSION_ERROR_BEGIN 0x04000000
@@ -488,6 +505,13 @@ enum hfi_picture_type {
#define HFI_INFO_DATA_CORRUPT 0x06000002
//TODO: Enable when firmware adds support for these
//#define HFI_INFO_NEGATIVE_TIMESTAMP 0x06000003
//#define HFI_INFO_BUFFER_OVERFLOW 0x06000004
//#define HFI_INFO_VCODEC_RESET 0x06000005
#define HFI_INFORMATION_END 0x06FFFFFF
#endif //__H_HFI_PROPERTY_H__

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@@ -29,14 +29,16 @@ int msm_v4l2_op_s_ctrl(struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_bitrate(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_entropy_mode(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_ltr_count(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_properties(struct msm_vidc_inst *inst);
int msm_vidc_adjust_v4l2_properties(struct msm_vidc_inst *inst);
int msm_vidc_set_u32(void *instance,
enum msm_vidc_inst_capability_type cap_id);
int msm_vidc_set_s32(void *instance,
enum msm_vidc_inst_capability_type cap_id);
int msm_vidc_set_array(void *instance,
enum msm_vidc_inst_capability_type cap_id);
int msm_vidc_set_fw_list(struct msm_vidc_inst *inst);
int msm_vidc_set_q16(void *instance,
enum msm_vidc_inst_capability_type cap_id);
int msm_vidc_set_v4l2_properties(struct msm_vidc_inst *inst);
int msm_vidc_v4l2_menu_to_hfi(struct msm_vidc_inst *inst,
enum msm_vidc_inst_capability_type cap_id, u32 *value);

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@@ -103,6 +103,7 @@ struct msm_vidc_inst {
struct msm_vidc_properties prop;
enum msm_vidc_stage_type stage;
enum msm_vidc_pipe_type pipe;
enum msm_vidc_quality_mode quality_mode;
struct msm_vidc_power power;
struct msm_vidc_buffers_info buffers;
struct msm_vidc_mappings_info mappings;

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@@ -40,6 +40,10 @@
#define DEFAULT_BSE_VPP_DELAY 2
#define MAX_CAP_PARENTS 16
#define MAX_CAP_CHILDREN 16
#define DEFAULT_BITSTREM_ALIGNMENT 16
#define H265_BITSTREM_ALIGNMENT 32
#define DEFAULT_MAX_HOST_BUF_COUNT 32
/* TODO
* #define MAX_SUPERFRAME_COUNT 32
*/
@@ -182,6 +186,11 @@ enum msm_vidc_pipe_type {
MSM_VIDC_PIPE_4 = 4,
};
enum msm_vidc_quality_mode {
MSM_VIDC_MAX_QUALITY_MODE = 0x1,
MSM_VIDC_POWER_SAVE_MODE = 0x2,
};
enum msm_vidc_core_capability_type {
CORE_CAP_NONE = 0,
ENC_CODECS,