qcacmn: add dedicated workqueue for Tx ring delayed reg write
Add delayed SRNG register writes support for Tx Ring, also add dedicated workqueue to do the delayed Tx SRNG register writes. Change-Id: I8dd157d341f3035e988804eab50d1ca681ab789b CRs-Fixed: 2868989
Цей коміт міститься в:

зафіксовано
snandini

джерело
fdf0a167e5
коміт
38af510319
@@ -25,8 +25,10 @@
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#include "qdf_mem.h"
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#include "qdf_nbuf.h"
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#include "pld_common.h"
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#ifdef FEATURE_HAL_DELAYED_REG_WRITE
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#if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
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defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
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#include "qdf_defer.h"
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#include "qdf_timer.h"
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#endif
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#define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_HAL, params)
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@@ -193,6 +195,35 @@ enum hal_srng_ring_id {
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HAL_SRNG_LMAC1_ID_END = 143
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};
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/* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
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enum hal_ring_type {
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REO_DST = 0,
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REO_EXCEPTION = 1,
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REO_REINJECT = 2,
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REO_CMD = 3,
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REO_STATUS = 4,
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TCL_DATA = 5,
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TCL_CMD_CREDIT = 6,
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TCL_STATUS = 7,
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CE_SRC = 8,
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CE_DST = 9,
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CE_DST_STATUS = 10,
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WBM_IDLE_LINK = 11,
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SW2WBM_RELEASE = 12,
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WBM2SW_RELEASE = 13,
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RXDMA_BUF = 14,
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RXDMA_DST = 15,
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RXDMA_MONITOR_BUF = 16,
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RXDMA_MONITOR_STATUS = 17,
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RXDMA_MONITOR_DST = 18,
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RXDMA_MONITOR_DESC = 19,
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DIR_BUF_RX_DMA_SRC = 20,
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#ifdef WLAN_FEATURE_CIF_CFR
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WIFI_POS_SRC,
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#endif
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MAX_RING_TYPES
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};
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#define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
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#define HAL_MAX_LMACS 3
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#define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
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@@ -228,7 +259,8 @@ typedef struct hal_ring_handle *hal_ring_handle_t;
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*/
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#define HAL_SRNG_FLUSH_EVENT BIT(0)
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#ifdef FEATURE_HAL_DELAYED_REG_WRITE
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#if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
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defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
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/**
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* struct hal_reg_write_q_elem - delayed register write queue element
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@@ -303,6 +335,21 @@ struct hal_reg_write_soc_stats {
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uint32_t max_q_depth;
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uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX];
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};
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#ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2
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struct hal_reg_write_tcl_stats {
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uint32_t wq_delayed;
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uint32_t wq_direct;
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uint32_t timer_enq;
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uint32_t timer_direct;
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uint32_t enq_timer_set;
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uint32_t direct_timer_set;
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uint32_t timer_reset;
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qdf_time_t enq_time;
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qdf_time_t deq_time;
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uint32_t sched_delay[REG_WRITE_SCHED_DELAY_HIST_MAX];
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};
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#endif
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#endif
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/* Common SRNG ring structure for source and destination rings */
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@@ -361,6 +408,9 @@ struct hal_srng {
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*/
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void *hwreg_base[MAX_SRNG_REG_GROUPS];
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/* Ring type/name */
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enum hal_ring_type ring_type;
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/* Source or Destination ring */
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enum hal_srng_dir ring_dir;
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@@ -418,10 +468,12 @@ struct hal_srng {
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unsigned long srng_event;
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/* last flushed time stamp */
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uint64_t last_flush_ts;
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#ifdef FEATURE_HAL_DELAYED_REG_WRITE
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#if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
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defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
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/* Previous hp/tp (based on ring dir) value written to the reg */
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uint32_t last_reg_wr_val;
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/* flag to indicate whether srng is already queued for delayed write */
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uint8_t reg_write_in_progress;
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/* srng specific delayed write stats */
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struct hal_reg_write_srng_stats wstats;
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#endif
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@@ -658,7 +710,8 @@ struct hal_hw_txrx_ops {
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*/
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struct hal_soc_stats {
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uint32_t reg_write_fail;
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#ifdef FEATURE_HAL_DELAYED_REG_WRITE
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#if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
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defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
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struct hal_reg_write_soc_stats wstats;
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#endif
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#ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
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@@ -773,7 +826,21 @@ struct hal_soc {
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qdf_atomic_t write_idx;
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/* read index used by worker thread to dequeue/write registers */
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uint32_t read_idx;
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#endif
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#endif /*FEATURE_HAL_DELAYED_REG_WRITE */
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#ifdef FEATURE_HAL_DELAYED_REG_WRITE_V2
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/* delayed work for TCL reg write to be queued into workqueue */
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qdf_work_t tcl_reg_write_work;
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/* workqueue for TCL delayed register writes */
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qdf_workqueue_t *tcl_reg_write_wq;
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/* flag denotes whether TCL delayed write work is active */
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qdf_atomic_t tcl_work_active;
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/* flag indiactes TCL write happening from direct context */
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bool tcl_direct;
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/* timer to handle the pending TCL reg writes */
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qdf_timer_t tcl_reg_write_timer;
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/* stats related to TCL reg write */
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struct hal_reg_write_tcl_stats tcl_stats;
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#endif /* FEATURE_HAL_DELAYED_REG_WRITE_V2 */
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qdf_atomic_t active_work_cnt;
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#ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
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struct shadow_reg_config
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@@ -782,7 +849,8 @@ struct hal_soc {
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#endif
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};
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#ifdef FEATURE_HAL_DELAYED_REG_WRITE
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#if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
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defined(FEATURE_HAL_DELAYED_REG_WRITE_V2)
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/**
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* hal_delayed_reg_write() - delayed regiter write
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* @hal_soc: HAL soc handle
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