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disp: msm: sde: restore qsync read pointer after IPC

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Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the
trigger window to be out of sync when power is restored
until the next vsync is received.

This change reads the panel read pointer and overrrides
the internal register to allow a frame to be picked up in
the current vsync cycle, but defers it to next vsync if it
comes later than the safe trigger window.

Change-Id: I741a91edcddc105eda34d875e8e1c32933b83d71
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This commit is contained in:
Amine Najahi
2022-10-20 11:06:29 -04:00
committed by Gerrit - the friendly Code Review server
parent d4a444a3d1
commit 386e77f95f
3 changed files with 93 additions and 1 deletions
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3
msm/sde/sde_encoder.h
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@@ -155,6 +155,8 @@ enum sde_enc_rc_states {
* @misr_frame_count: misr frame count before start capturing the data
* @idle_pc_enabled: indicate if idle power collapse is enabled
* currently. This can be controlled by user-mode
* @restore_te_rd_ptr: flag to indicate that te read pointer value must
* be restored after idle power collapse
* @rc_lock: resource control mutex lock to protect
* virt encoder over various state changes
* @rc_state: resource controller state
@@ -242,6 +244,7 @@ struct sde_encoder_virt {
struct input_handler *input_handler;
bool vblank_enabled;
bool idle_pc_restore;
bool restore_te_rd_ptr;
enum frame_trigger_mode_type frame_trigger_mode;
bool dynamic_hdr_updated;