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qcacmn: Register IRQ for near full irq

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WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.

Register for the near full irq and add the necessary
ext groups for these near-full irqs.

Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
This commit is contained in:
Rakesh Pillai
2021-03-23 05:32:56 -07:00
committed by Madan Koyyalamudi
parent cebffa806d
commit 37e2c6d9ed
11 changed files with 836 additions and 105 deletions
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45
hal/wifi3.0/hal_hw_headers.h
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@@ -86,6 +86,12 @@
#define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
#define HAL_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
#define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_SHFT 0x0
#define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff
#define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 0x8
#define HAL_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100
#define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
#define HAL_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
@@ -104,6 +110,12 @@
#define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
#define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24
#define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000
#define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0
#define HAL_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff
#define HAL_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
#define HAL_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
@@ -183,11 +195,15 @@
#define HP_ADDR_LSB_GROUP R0
#define HP_ADDR_MSB_GROUP R0
#define PRODUCER_INT_SETUP_GROUP R0
#define PRODUCER_INT2_SETUP_GROUP R0
#define PRODUCER_INT_STATUS_GROUP R0
#define PRODUCER_FULL_COUNTER_GROUP R0
#define MSI1_BASE_LSB_GROUP R0
#define MSI1_BASE_MSB_GROUP R0
#define MSI1_DATA_GROUP R0
#define MSI2_BASE_LSB_GROUP R0
#define MSI2_BASE_MSB_GROUP R0
#define MSI2_DATA_GROUP R0
#define HP_TP_SW_OFFSET_GROUP R0
#define TP_ADDR_LSB_GROUP R0
#define TP_ADDR_MSB_GROUP R0
@@ -314,35 +330,6 @@
#define HAL_SRNG_CONFIG(_hal_soc, _ring_type) \
(&_hal_soc->hw_srng_table[_ring_type])
enum SRNG_REGISTERS {
DST_HP = 0,
DST_TP,
DST_ID,
DST_MISC,
DST_HP_ADDR_LSB,
DST_HP_ADDR_MSB,
DST_MSI1_BASE_LSB,
DST_MSI1_BASE_MSB,
DST_MSI1_DATA,
DST_BASE_LSB,
DST_BASE_MSB,
DST_PRODUCER_INT_SETUP,
SRC_HP,
SRC_TP,
SRC_ID,
SRC_MISC,
SRC_TP_ADDR_LSB,
SRC_TP_ADDR_MSB,
SRC_MSI1_BASE_LSB,
SRC_MSI1_BASE_MSB,
SRC_MSI1_DATA,
SRC_BASE_LSB,
SRC_BASE_MSB,
SRC_CONSUMER_INT_SETUP_IX0,
SRC_CONSUMER_INT_SETUP_IX1,
};
/**
* hal_set_link_desc_addr - Setup link descriptor in a buffer_addr_info
* HW structure