qcacmn: Register IRQ for near full irq
WCN7850 has support for near full indication for the consumer srngs. This interrupt is used to take preventive actions to avoid ring full watchdog irq trigger. Register for the near full irq and add the necessary ext groups for these near-full irqs. Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c CRs-Fixed: 2965081
This commit is contained in:

committed by
Madan Koyyalamudi

parent
cebffa806d
commit
37e2c6d9ed
@@ -292,6 +292,65 @@ void hal_srng_src_hw_init_generic(struct hal_soc *hal,
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SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
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}
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#ifdef WLAN_FEATURE_NEAR_FULL_IRQ
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/**
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* hal_srng_dst_msi2_setup() - Configure MSI2 register for a SRNG
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* @srng: SRNG handle
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*
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* Return: None
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*/
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static inline void hal_srng_dst_msi2_setup(struct hal_srng *srng)
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{
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uint32_t reg_val = 0;
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if (srng->u.dst_ring.nf_irq_support) {
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SRNG_DST_REG_WRITE(srng, MSI2_BASE_LSB,
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srng->msi2_addr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_DST_FLD(MSI2_BASE_MSB, ADDR),
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(uint64_t)(srng->msi2_addr) >> 32) |
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SRNG_SM(SRNG_DST_FLD(MSI2_BASE_MSB,
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MSI2_ENABLE), 1);
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SRNG_DST_REG_WRITE(srng, MSI2_BASE_MSB, reg_val);
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SRNG_DST_REG_WRITE(srng, MSI2_DATA,
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qdf_cpu_to_le32(srng->msi2_data));
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}
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}
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/**
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* hal_srng_dst_near_full_int_setup() - Configure near-full params for SRNG
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* @srng: SRNG handle
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*
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* Return: None
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*/
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static inline void hal_srng_dst_near_full_int_setup(struct hal_srng *srng)
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{
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uint32_t reg_val = 0;
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if (srng->u.dst_ring.nf_irq_support) {
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if (srng->intr_timer_thres_us) {
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reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT2_SETUP,
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INTERRUPT2_TIMER_THRESHOLD),
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srng->intr_timer_thres_us >> 3);
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}
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reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT2_SETUP,
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HIGH_THRESHOLD),
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srng->u.dst_ring.high_thresh *
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srng->entry_size);
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}
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SRNG_DST_REG_WRITE(srng, PRODUCER_INT2_SETUP, reg_val);
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}
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#else
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static inline void hal_srng_dst_msi2_setup(struct hal_srng *srng)
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{
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}
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static inline void hal_srng_dst_near_full_int_setup(struct hal_srng *srng)
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{
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}
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#endif
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/**
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* hal_srng_dst_hw_init - Private function to initialize SRNG
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* destination ring HW
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@@ -317,6 +376,8 @@ void hal_srng_dst_hw_init_generic(struct hal_soc *hal,
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SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
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SRNG_DST_REG_WRITE(srng, MSI1_DATA,
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qdf_cpu_to_le32(srng->msi_data));
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hal_srng_dst_msi2_setup(srng);
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}
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SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
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@@ -351,6 +412,14 @@ void hal_srng_dst_hw_init_generic(struct hal_soc *hal,
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}
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SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val);
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/**
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* Near-Full Interrupt setup:
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* Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
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* if level mode is required
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*/
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hal_srng_dst_near_full_int_setup(srng);
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hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
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((unsigned long)(srng->u.dst_ring.hp_addr) -
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(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
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