qcacmn: Drain group tasklets and reg write work for runtime PM

Currently as part of runtime PM, only the active
tasklets are being drained. For chips eg. QCA6390,
QCA6490 etc, there are grp_tasklets and delayed reg
write work which has to be drained before entering
runtime PM.

Add the logic to drain all the possible tasks
before entering runtime PM.

Change-Id: Ieb486f00fffd7346dcdc1faea6fed5850ef6daf7
CRs-Fixed: 2676000

hal/wifi3.0/hal_api.h

@@ -551,6 +551,16 @@ void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl);
  * Return: none
  */
 void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl);
+
+/**
+ * hal_get_reg_write_pending_work() - get the number of entries
+ *		pending in the workqueue to be processed.
+ * @hal_soc: HAL soc handle
+ *
+ * Returns: the number of entries pending to be processed
+ */
+int hal_get_reg_write_pending_work(void *hal_soc);
+
 #else
 static inline void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
 {
@@ -559,6 +569,11 @@ static inline void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
 static inline void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
 {
 }
+
+static inline int hal_get_reg_write_pending_work(void *hal_soc)
+{
+	return 0;
+}
 #endif
 
 /**

hal/wifi3.0/hal_internal.h

@@ -718,6 +718,7 @@ struct hal_soc {
 	/* read index used by worker thread to dequeue/write registers */
 	uint32_t read_idx;
 #endif
+	qdf_atomic_t active_work_cnt;
 };
 
 #ifdef FEATURE_HAL_DELAYED_REG_WRITE

hal/wifi3.0/hal_srng.c

@@ -480,6 +480,7 @@ static void hal_reg_write_work(void *arg)
 		hal_verbose_debug("read_idx %u srng 0x%x, addr 0x%pK dequeue_val %u sched delay %llu us",
 				  hal->read_idx, ring_id, addr, write_val, delta_us);
 
+		qdf_atomic_dec(&hal->active_work_cnt);
 		hal->read_idx = (hal->read_idx + 1) &
 					(HAL_REG_WRITE_QUEUE_LEN - 1);
 		q_elem = &hal->reg_write_queue[(hal->read_idx)];
@@ -560,6 +561,7 @@ static void hal_reg_write_enqueue(struct hal_soc *hal_soc,
 	q_elem->valid = true;
 
 	srng->reg_write_in_progress  = true;
+	qdf_atomic_inc(&hal_soc->active_work_cnt);
 
 	hal_verbose_debug("write_idx %u srng ring id 0x%x addr 0x%pK val %u",
 			  write_idx, srng->ring_id, addr, value);
@@ -686,6 +688,14 @@ void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
 		  hist[REG_WRITE_SCHED_DELAY_SUB_5000us],
 		  hist[REG_WRITE_SCHED_DELAY_GT_5000us]);
 }
+
+int hal_get_reg_write_pending_work(void *hal_soc)
+{
+	struct hal_soc *hal = (struct hal_soc *)hal_soc;
+
+	return qdf_atomic_read(&hal->active_work_cnt);
+}
+
 #else
 static inline QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
 {
@@ -770,6 +780,7 @@ void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
 
 	qdf_minidump_log(hal, sizeof(*hal), "hal_soc");
 
+	qdf_atomic_init(&hal->active_work_cnt);
 	hal_delayed_reg_write_init(hal);
 
 	return (void *)hal;