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msm: camera: csiphy: Update phy sequence for bengal

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Toggle reset register  in common and reset programming sequence.

CRs-Fixed: 2615460
Change-Id: Iba17fa3b2014be0bc27236169cf8456a7f8ededd
Signed-off-by: Tony Lijo Jose <tjose@codeaurora.org>
This commit is contained in:
Tony Lijo Jose
2020-02-03 12:42:03 +05:30
committed by Gerrit - the friendly Code Review server
parent 6bc220f0a7
commit 37b7384396
1 changed files with 7 additions and 3 deletions
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10
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h
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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_CSIPHY_2_0_HWREG_H_
@@ -12,8 +12,8 @@ struct csiphy_reg_parms_t csiphy_v2_0 = {
.mipi_csiphy_interrupt_status0_addr = 0x8B0,
.mipi_csiphy_interrupt_clear0_addr = 0x858,
.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
.csiphy_common_array_size = 6,
.csiphy_reset_array_size = 3,
.csiphy_common_array_size = 8,
.csiphy_reset_array_size = 5,
.csiphy_2ph_config_array_size = 15,
.csiphy_3ph_config_array_size = 17,
.csiphy_2ph_clock_lane = 0x1,
@@ -24,6 +24,8 @@ struct csiphy_reg_t csiphy_common_reg_2_0[] = {
{0x0814, 0x00, 0x00, CSIPHY_LANE_ENABLE},
{0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x081C, 0x06, 0x00, CSIPHY_3PH_REGS},
{0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0164, 0x00, 0x00, CSIPHY_2PH_REGS},
{0x0364, 0x00, 0x00, CSIPHY_2PH_REGS},
{0x0564, 0x00, 0x00, CSIPHY_2PH_REGS},
@@ -33,6 +35,8 @@ struct csiphy_reg_t csiphy_reset_reg_2_0[] = {
{0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE},
{0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
};
struct csiphy_reg_t csiphy_irq_reg_2_0[] = {