msm: eva: Recover EVA SMMU fault

Needs extra change to enable EVA SMMU fault. This change clears
all the obstacles to achieve the goal.

Change-Id: Ia93ff2132ff53741f3c20d4271083f6f93824cac
Signed-off-by: George Shen <[email protected]>

msm/eva/cvp_hfi.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <asm/memory.h>
@@ -2342,6 +2343,7 @@ static int iris_hfi_core_release(void *dev)
 	struct iris_hfi_device *device = dev;
 	struct cvp_hal_session *session, *next;
 	struct dev_pm_qos_request *qos_hdl;
+	u32 ipcc_iova;
 
 	if (!device) {
 		dprintk(CVP_ERR, "invalid device\n");
@@ -2370,6 +2372,8 @@ static int iris_hfi_core_release(void *dev)
 	__dsp_shutdown(device);
 
 	__disable_subcaches(device);
+	ipcc_iova = __read_register(device, CVP_MMAP_ADDR);
+	msm_cvp_unmap_ipcc_regs(ipcc_iova);
 	__unload_fw(device);
 	__hwfence_regs_unmap(device);
 
@@ -2521,6 +2525,11 @@ static int iris_debug_hook(void *device)
 		dprintk(CVP_ERR, "%s Invalid device\n", __func__);
 		return -ENODEV;
 	}
+	__write_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0x11);
+	__write_register(dev, CVP_WRAPPER_TZ_CPU_CLOCK_CONFIG, 0x1);
+	dprintk(CVP_ERR, "Halt Tensilica and core and axi\n");
+	return 0;
+
 	/******* FDU & MPU *****/
 #define CVP0_CVP_SS_FDU_SECURE_ENABLE 0x90
 #define CVP0_CVP_SS_MPU_SECURE_ENABLE 0x94

msm/eva/cvp_hfi_io.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef __CVP_HFI_IO_H__
@@ -111,6 +112,7 @@
 
 #define CVP_WRAPPER_TZ_BASE_OFFS		0x000C0000
 
+#define CVP_WRAPPER_TZ_CPU_CLOCK_CONFIG	(CVP_WRAPPER_TZ_BASE_OFFS)
 #define CVP_WRAPPER_INTR_CLEAR_A2HWD_BMSK	0x10
 #define CVP_WRAPPER_INTR_CLEAR_A2HWD_SHFT	0x4
 #define CVP_WRAPPER_INTR_CLEAR_A2H_BMSK	0x4

msm/eva/cvp_smem.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/dma-buf.h>
@@ -606,3 +607,36 @@ int msm_cvp_map_ipcc_regs(u32 *iova)
 	}
 	return 0;
 }
+
+int msm_cvp_unmap_ipcc_regs(u32 iova)
+{
+	struct context_bank_info *cb;
+	struct msm_cvp_core *core;
+	struct cvp_hfi_device *hfi_ops;
+	struct iris_hfi_device *dev = NULL;
+	u32 size;
+
+	core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list);
+	if (core) {
+		hfi_ops = core->device;
+		if (hfi_ops)
+			dev = hfi_ops->hfi_device_data;
+	}
+
+	if (!dev)
+		return -EINVAL;
+
+	size = dev->res->ipcc_reg_size;
+
+	if (!iova || !size)
+		return -EINVAL;
+
+	cb = msm_cvp_smem_get_context_bank(dev->res, 0);
+	if (!cb) {
+		dprintk(CVP_ERR, "%s: fail to get context bank\n", __func__);
+		return -EINVAL;
+	}
+	dma_unmap_resource(cb->dev, iova, size, DMA_BIDIRECTIONAL, 0);
+
+	return 0;
+}

msm/eva/msm_cvp_buf.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _MSM_CVP_BUF_H_
@@ -194,6 +195,7 @@ int msm_cvp_smem_cache_operations(struct dma_buf *dbuf,
 				unsigned long offset,
 				unsigned long size);
 int msm_cvp_map_ipcc_regs(u32 *iova);
+int msm_cvp_unmap_ipcc_regs(u32 iova);
 
 /* CVP driver internal buffer management functions*/
 struct cvp_internal_buf *cvp_allocate_arp_bufs(struct msm_cvp_inst *inst,

msm/eva/msm_cvp_res_parse.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/iommu.h>
@@ -1038,12 +1039,16 @@ int msm_cvp_smmu_fault_handler(struct iommu_domain *domain,
 		return -EINVAL;
 	}
 
+	dprintk(CVP_ERR, "%s - faulting address: %lx fault cnt %d\n",
+			__func__, iova, core->smmu_fault_count);
+	if (core->smmu_fault_count > 0) {
+		core->smmu_fault_count++;
+		return -ENOSYS;
+	}
 	mutex_lock(&core->lock);
 	core->smmu_fault_count++;
 	if (!core->last_fault_addr)
 		core->last_fault_addr = iova;
-	dprintk(CVP_ERR, "%s - faulting address: %lx, %d\n",
-		__func__, iova, core->smmu_fault_count);
 
 	log = (core->log.snapshot_index > 0)? false : true;
 	list_for_each_entry(inst, &core->instances, list) {