disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
During DMS, when tear check registers are updated near rd_ptr line count, it was resulting in a spurious rd_ptr_irq to which frame is getting latched and causing tearing on the screen. This change updates TEAR_SYNC_WRCOUNT register before disabling the vsync counter and adds a spinlock to avoid pre-emption. Change-Id: I986dc3ce6fb3da5fed758c2f50562df44f2ab557 Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Cette révision appartient à :
@@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/iopoll.h>
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@@ -616,10 +617,12 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
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{
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struct sde_hw_blk_reg_map *c;
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u32 cfg = 0;
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spinlock_t tearcheck_spinlock;
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if (!intf)
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return -EINVAL;
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spin_lock_init(&tearcheck_spinlock);
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c = &intf->hw;
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if (te->hw_vsync_mode)
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@@ -627,6 +630,14 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
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cfg |= te->vsync_count;
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/*
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* Local spinlock is acquired here to avoid pre-emption
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* as below register programming should be completed in
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* less than 2^16 vsync clk cycles.
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*/
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spin_lock(&tearcheck_spinlock);
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SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,
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(te->start_pos + te->sync_threshold_start + 1));
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SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
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wmb(); /* disable vsync counter before updating single buffer registers */
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SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
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@@ -637,10 +648,9 @@ static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
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SDE_REG_WRITE(c, INTF_TEAR_SYNC_THRESH,
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((te->sync_threshold_continue << 16) |
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te->sync_threshold_start));
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SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT,
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(te->start_pos + te->sync_threshold_start + 1));
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cfg |= BIT(19); /* VSYNC_COUNTER_EN */
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SDE_REG_WRITE(c, INTF_TEAR_SYNC_CONFIG_VSYNC, cfg);
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spin_unlock(&tearcheck_spinlock);
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return 0;
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}
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