fw-api: CL 7433623 - update fw common interface files
Change-Id: I0d6a403ac347fca1665fbd2ccaaf64d7026f5a96 HTT: add def of htt_ul_ofdma_user_info_v0 CRs-Fixed: 2262693
This commit is contained in:
spuligil
260
fw/htt.h
260
fw/htt.h
@@ -186,9 +186,11 @@
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* 3.66 Add HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND msg.
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* Add PKT_CAPTURE_MODE flag within HTT_T2H TX_I_ORD_PADDR_IND msg.
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* 3.67 Add drop threshold field to HTT_H2T RX_RING_SELECTION_CFG msg.
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* 3.68 Add ipa_drop threshold fields to HTT_H2T_MSG_TYPE_SRING_SETUP
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* 3.69 Add htt_ul_ofdma_user_info_v0 defs
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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#define HTT_CURRENT_VERSION_MINOR 68
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#define HTT_CURRENT_VERSION_MINOR 69
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#define HTT_NUM_TX_FRAG_DESC 1024
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@@ -4299,9 +4301,9 @@ PREPACK struct htt_wdi_ipa_op_request_t
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* setup message
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*
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* The message would appear as follows:
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* |31 24|23 20|19|18 16|15|14 8|7 0|
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* |--------------- +-----------------+----------------+------------------|
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* | ring_type | ring_id | pdev_id | msg_type |
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* |31 24|23 21|20|19|18 16|15|14 8|7 0|
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* |--------------- +-----------------+-----------------+-----------------|
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* | ring_type | ring_id | pdev_id | msg_type |
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* |----------------------------------------------------------------------|
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* | ring_base_addr_lo |
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* |----------------------------------------------------------------------|
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@@ -4325,12 +4327,15 @@ PREPACK struct htt_wdi_ipa_op_request_t
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* |----------------------------------------------------------------------|
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* | intr_timer_th |IM| intr_batch_counter_th |
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* |----------------------------------------------------------------------|
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* | reserved |RR|PTCF| intr_low_threshold |
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* | reserved |ID|RR| PTCF| intr_low_threshold |
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* |----------------------------------------------------------------------|
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* | reserved |IPA drop thres hi|IPA drop thres lo|
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* |----------------------------------------------------------------------|
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* Where
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* IM = sw_intr_mode
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* RR = response_required
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* PTCF = prefetch_timer_cfg
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* IP = IPA drop flag
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*
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* The message is interpreted as follows:
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* dword0 - b'0:7 - msg_type: This will be set to
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@@ -12328,4 +12333,249 @@ PREPACK struct htt_t2h_msg_bkpressure_event_ind_t {
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A_UINT32 backpressure_time_ms; /* Time in milliseconds for which backpressure is seen continuously */
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} POSTPACK;
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/*
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* Defines two 32 bit words that can be used by the target to indicate a per
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* user RU allocation and rate information.
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*
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* This information is currently provided in the "sw_response_reference_ptr"
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* (word 0) and "sw_response_reference_ptr_ext" (word 1) fields of the
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* "rx_ppdu_end_user_stats" TLV.
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*
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* VALID:
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* The consumer of these words must explicitly check the valid bit,
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* and only attempt interpretation of any of the remaining fields if
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* the valid bit is set to 1.
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*
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* VERSION:
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* The consumer of these words must also explicitly check the version bit,
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* and only use the V0 definition if the VERSION field is set to 0.
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*
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* Version 1 is currently undefined, with the exception of the VALID and
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* VERSION fields.
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*
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* Version 0:
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*
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* The fields below are duplicated per BW.
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*
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* The consumer must determine which BW field to use, based on the UL OFDMA
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* PPDU BW indicated by HW.
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*
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* RU_START: RU26 start index for the user.
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* Note that this is always using the RU26 index, regardless
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* of the actual RU assigned to the user
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* (i.e. the second RU52 is RU_START 2, RU_SIZE
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* HTT_UL_OFDMA_V0_RU_SIZE_RU_52)
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*
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* For example, 20MHz (the value in the top row is RU_START)
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*
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* RU Size 0 (26): |0|1|2|3|4|5|6|7|8|
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* RU Size 1 (52): | | | | | |
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* RU Size 2 (106): | | | |
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* RU Size 3 (242): | |
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*
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* RU_SIZE: Indicates the RU size, as defined by enum
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* htt_ul_ofdma_user_info_ru_size.
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*
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* LDPC: LDPC enabled (if 0, BCC is used)
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*
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* DCM: DCM enabled
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*
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* |31 | 30|29 23|22 19|18 16|15 9| 8 | 7 |6 3|2 0|
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* |---------------------------------+--------------------------------|
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* |Ver|Valid| FW internal |
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* |---------------------------------+--------------------------------|
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* | reserved |Trig Type|RU SIZE| RU START |DCM|LDPC|MCS |NSS|
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* |---------------------------------+--------------------------------|
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*/
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enum htt_ul_ofdma_user_info_ru_size {
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HTT_UL_OFDMA_V0_RU_SIZE_RU_26,
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HTT_UL_OFDMA_V0_RU_SIZE_RU_52,
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HTT_UL_OFDMA_V0_RU_SIZE_RU_106,
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HTT_UL_OFDMA_V0_RU_SIZE_RU_242,
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HTT_UL_OFDMA_V0_RU_SIZE_RU_484,
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HTT_UL_OFDMA_V0_RU_SIZE_RU_996,
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HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2
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};
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/* htt_up_ofdma_user_info_v0 provides an abstract view of the info */
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struct htt_ul_ofdma_user_info_v0 {
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A_UINT32 word0;
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A_UINT32 word1;
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};
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/* htt_up_ofdma_user_info_v0_bitmap shows what bitfields are within the info */
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PREPACK struct htt_ul_ofdma_user_info_v0_bitmap {
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union {
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A_UINT32 word0;
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struct {
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A_UINT32 w0_fw_rsvd:30;
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A_UINT32 w0_valid:1;
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A_UINT32 w0_version:1;
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};
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};
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union {
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A_UINT32 word1;
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struct {
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A_UINT32 w1_nss:3;
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A_UINT32 w1_mcs:4;
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A_UINT32 w1_ldpc:1;
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A_UINT32 w1_dcm:1;
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A_UINT32 w1_ru_start:7;
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A_UINT32 w1_ru_size:3;
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A_UINT32 w1_trig_type:4;
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A_UINT32 w1_unused:9;
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};
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};
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} POSTPACK;
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enum HTT_UL_OFDMA_TRIG_TYPE {
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HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BASIC = 0,
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HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BFRP,
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HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_BAR,
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HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_RTS_CTS,
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HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BSR,
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};
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#define HTT_UL_OFDMA_USER_INFO_V0_SZ (sizeof(struct htt_ul_ofdma_user_info_v0))
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M 0x80000000
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S 31
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M 0x00000007
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S 0
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M 0x00000078
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S 3
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M 0x00000080
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S 7
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M 0x00000100
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S 8
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M 0x0000fe00
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S 9
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M 0x00070000
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S 16
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M 0x00780000
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S 19
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_M 0xff800000
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_S 23
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/*--- word 0 ---*/
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)); \
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} while (0)
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VALID, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)); \
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} while (0)
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VER, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)); \
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} while (0)
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/*--- word 1 ---*/
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_NSS, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)); \
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} while (0)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_MCS, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)); \
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} while (0)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)); \
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} while (0)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_DCM, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)); \
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} while (0)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)); \
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} while (0)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)); \
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} while (0)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_GET(word) \
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(((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S)
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#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_SET(word, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP, _val); \
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((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP_S)); \
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} while (0)
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#endif
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