qcacmn: Add hal_rx_get_rx_sequence API

Add hal_rx_get_rx_sequence API to retrieve
rx sequence value based on the chipset.

Change-Id: I8377b96dfe04e9695a183482d9fcc4a804f845e0
CRs-Fixed: 2522133
This commit is contained in:
Venkata Sharath Chandra Manchala
2019-09-25 19:00:14 -07:00
committed by nshrivas
parent f73d891115
commit 36fd40ab6e
12 changed files with 110 additions and 65 deletions

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@@ -1079,7 +1079,8 @@ void dp_rx_process_mic_error(struct dp_soc *soc, qdf_nbuf_t nbuf,
if (fragno) { if (fragno) {
tid = hal_rx_mpdu_start_tid_get(soc->hal_soc, tid = hal_rx_mpdu_start_tid_get(soc->hal_soc,
qdf_nbuf_data(nbuf)); qdf_nbuf_data(nbuf));
rx_seq = hal_rx_get_rx_sequence(qdf_nbuf_data(nbuf)); rx_seq = hal_rx_get_rx_sequence(soc->hal_soc,
qdf_nbuf_data(nbuf));
status = dp_rx_defrag_add_last_frag(soc, peer, status = dp_rx_defrag_add_last_frag(soc, peer,
tid, rx_seq, nbuf); tid, rx_seq, nbuf);

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@@ -43,7 +43,6 @@
#else #else
#include "wfss_ce_reg_seq_hwioreg.h" #include "wfss_ce_reg_seq_hwioreg.h"
#endif /* QCA_WIFI_QCA6490 */ #endif /* QCA_WIFI_QCA6490 */
#include "wfss_ce_reg_seq_hwioreg.h"
#include "wbm_link_descriptor_ring.h" #include "wbm_link_descriptor_ring.h"
#include "wbm_reg_seq_hwioreg.h" #include "wbm_reg_seq_hwioreg.h"
#include "wbm_buffer_ring.h" #include "wbm_buffer_ring.h"

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@@ -449,6 +449,7 @@ struct hal_hw_txrx_ops {
bool *flow_timeout, bool *flow_timeout,
uint32_t *flow_index); uint32_t *flow_index);
uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf); uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf);
uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf);
}; };
/** /**

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@@ -900,12 +900,6 @@ hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata)
HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata);
} }
#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
/** /**
* LRO information needed from the TLVs * LRO information needed from the TLVs
*/ */
@@ -1420,12 +1414,6 @@ hal_rx_msdu_start_get_pkt_type(uint8_t *buf)
return pkt_type; return pkt_type;
} }
#define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_2_TO_DS_OFFSET)), \
RX_MPDU_INFO_2_TO_DS_MASK, \
RX_MPDU_INFO_2_TO_DS_LSB))
/* /*
* hal_rx_mpdu_get_tods(): API to get the tods info * hal_rx_mpdu_get_tods(): API to get the tods info
* from rx_mpdu_start * from rx_mpdu_start
@@ -1459,12 +1447,6 @@ hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf); return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf);
} }
#define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
#define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
@@ -2517,32 +2499,9 @@ struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs)
return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
} }
/**
* hal_rx_get_rx_sequence(): Function to retrieve rx sequence number
*
* @nbuf: Network buffer
* Returns: rx sequence number
*/
#define DOT11_SEQ_FRAG_MASK 0x000f #define DOT11_SEQ_FRAG_MASK 0x000f
#define DOT11_FC1_MORE_FRAG_OFFSET 0x04 #define DOT11_FC1_MORE_FRAG_OFFSET 0x04
#define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
static inline
uint16_t hal_rx_get_rx_sequence(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
uint16_t seq_number = 0;
seq_number = HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
return seq_number;
}
/** /**
* hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number
* *
@@ -3407,4 +3366,13 @@ uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl,
return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf); return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf);
} }
static inline
uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl,
uint8_t *buf)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
return hal_soc->ops->hal_rx_get_rx_sequence(buf);
}
#endif /* _HAL_RX_H */ #endif /* _HAL_RX_H */

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@@ -962,6 +962,21 @@ hal_rx_tlv_get_tcp_chksum_6290(uint8_t *buf)
return HAL_RX_TLV_GET_TCP_CHKSUM(buf); return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
} }
/**
* hal_rx_get_rx_sequence_6290(): Function to retrieve rx sequence number
* @nbuf: Network buffer
*
* Return: rx sequence number
*/
static
uint16_t hal_rx_get_rx_sequence_6290(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
}
struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
hal_srng_dst_hw_init_generic, hal_srng_dst_hw_init_generic,
@@ -1046,6 +1061,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
hal_rx_msdu_cce_metadata_get_6290, hal_rx_msdu_cce_metadata_get_6290,
hal_rx_msdu_get_flow_params_6290, hal_rx_msdu_get_flow_params_6290,
hal_rx_tlv_get_tcp_chksum_6290, hal_rx_tlv_get_tcp_chksum_6290,
hal_rx_get_rx_sequence_6290,
}; };
struct hal_hw_srng_config hw_srng_table_6290[] = { struct hal_hw_srng_config hw_srng_table_6290[] = {

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@@ -958,6 +958,21 @@ hal_rx_tlv_get_tcp_chksum_6390(uint8_t *buf)
return HAL_RX_TLV_GET_TCP_CHKSUM(buf); return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
} }
/**
* hal_rx_get_rx_sequence_6390(): Function to retrieve rx sequence number
*
* @nbuf: Network buffer
* Returns: rx sequence number
*/
static
uint16_t hal_rx_get_rx_sequence_6390(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
}
struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
hal_srng_dst_hw_init_generic, hal_srng_dst_hw_init_generic,
@@ -1042,6 +1057,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
hal_rx_msdu_cce_metadata_get_6390, hal_rx_msdu_cce_metadata_get_6390,
hal_rx_msdu_get_flow_params_6390, hal_rx_msdu_get_flow_params_6390,
hal_rx_tlv_get_tcp_chksum_6390, hal_rx_tlv_get_tcp_chksum_6390,
hal_rx_get_rx_sequence_6390,
}; };
struct hal_hw_srng_config hw_srng_table_6390[] = { struct hal_hw_srng_config hw_srng_table_6390[] = {

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@@ -1275,10 +1275,20 @@ hal_rx_tlv_get_tcp_chksum_6490(uint8_t *buf)
return HAL_RX_TLV_GET_TCP_CHKSUM(buf); return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
} }
struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = { /**
/* tx */ * hal_rx_get_rx_sequence_6490(): Function to retrieve rx sequence number
/* rx */ *
}; * @nbuf: Network buffer
* Returns: rx sequence number
*/
static
uint16_t hal_rx_get_rx_sequence_6490(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
}
struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -1325,6 +1335,7 @@ struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
hal_rx_get_rx_fragment_number_6490, hal_rx_get_rx_fragment_number_6490,
hal_rx_msdu_end_da_is_mcbc_get_6490, hal_rx_msdu_end_da_is_mcbc_get_6490,
hal_rx_msdu_end_sa_is_valid_get_6490, hal_rx_msdu_end_sa_is_valid_get_6490,
hal_rx_msdu_end_sa_idx_get_6490,
hal_rx_desc_is_first_msdu_6490, hal_rx_desc_is_first_msdu_6490,
hal_rx_msdu_end_l3_hdr_padding_get_6490, hal_rx_msdu_end_l3_hdr_padding_get_6490,
hal_rx_encryption_info_valid_6490, hal_rx_encryption_info_valid_6490,
@@ -1364,6 +1375,7 @@ struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
hal_rx_msdu_cce_metadata_get_6490, hal_rx_msdu_cce_metadata_get_6490,
NULL, NULL,
hal_rx_tlv_get_tcp_chksum_6490, hal_rx_tlv_get_tcp_chksum_6490,
hal_rx_get_rx_sequence_6490,
}; };
struct hal_hw_srng_config hw_srng_table_6490[] = { struct hal_hw_srng_config hw_srng_table_6490[] = {

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@@ -350,3 +350,4 @@ RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \ RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \
RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \ RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \
RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB)) RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB))
#endif

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@@ -164,20 +164,3 @@ static void hal_tx_desc_set_lmac_id_6490(void *desc, uint8_t lmac_id)
HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |= HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id); HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
} }
/**
* hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor
* @desc: Handle to Tx Descriptor
* @en: For raw WiFi frames, this indicates transmission to a mesh STA,
* enabling the interpretation of the 'Mesh Control Present' bit
* (bit 8) of QoS Control (otherwise this bit is ignored),
* For native WiFi frames, this indicates that a 'Mesh Control' field
* is present between the header and the LLC.
*
* Return: void
*/
inline void hal_tx_desc_set_mesh_en(void *desc, uint8_t en)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |=
HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
}

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@@ -584,7 +584,7 @@ static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl,
RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB));
if (qos_control_valid) if (qos_control_valid)
return hal_rx_mpdu_start_tid_get_8074v1(buf); return hal_rx_mpdu_start_tid_get_8074(buf);
return HAL_RX_NON_QOS_TID; return HAL_RX_NON_QOS_TID;
} }
@@ -958,6 +958,21 @@ hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf)
return HAL_RX_TLV_GET_TCP_CHKSUM(buf); return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
} }
/**
* hal_rx_get_rx_sequence_8074v1(): Function to retrieve rx sequence number
*
* @nbuf: Network buffer
* Returns: rx sequence number
*/
static
uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
}
struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -1043,6 +1058,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
hal_rx_msdu_cce_metadata_get_8074v1, hal_rx_msdu_cce_metadata_get_8074v1,
hal_rx_msdu_get_flow_params_8074v1, hal_rx_msdu_get_flow_params_8074v1,
hal_rx_tlv_get_tcp_chksum_8074v1, hal_rx_tlv_get_tcp_chksum_8074v1,
hal_rx_get_rx_sequence_8074v1,
}; };
struct hal_hw_srng_config hw_srng_table_8074[] = { struct hal_hw_srng_config hw_srng_table_8074[] = {

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@@ -955,6 +955,21 @@ hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf)
return HAL_RX_TLV_GET_TCP_CHKSUM(buf); return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
} }
/**
* hal_rx_get_rx_sequence_8074v2(): Function to retrieve rx sequence number
*
* @nbuf: Network buffer
* Returns: rx sequence number
*/
static
uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
}
struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -1041,6 +1056,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
hal_rx_msdu_cce_metadata_get_8074v2, hal_rx_msdu_cce_metadata_get_8074v2,
hal_rx_msdu_get_flow_params_8074v2, hal_rx_msdu_get_flow_params_8074v2,
hal_rx_tlv_get_tcp_chksum_8074v2, hal_rx_tlv_get_tcp_chksum_8074v2,
hal_rx_get_rx_sequence_8074v2,
}; };
struct hal_hw_srng_config hw_srng_table_8074v2[] = { struct hal_hw_srng_config hw_srng_table_8074v2[] = {

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@@ -964,6 +964,21 @@ hal_rx_tlv_get_tcp_chksum_9000(uint8_t *buf)
return HAL_RX_TLV_GET_TCP_CHKSUM(buf); return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
} }
/**
* hal_rx_get_rx_sequence_9000(): Function to retrieve rx sequence number
*
* @nbuf: Network buffer
* Returns: rx sequence number
*/
static
uint16_t hal_rx_get_rx_sequence_9000(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
}
struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -1050,6 +1065,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
hal_rx_msdu_cce_metadata_get_9000, hal_rx_msdu_cce_metadata_get_9000,
hal_rx_msdu_get_flow_params_9000, hal_rx_msdu_get_flow_params_9000,
hal_rx_tlv_get_tcp_chksum_9000, hal_rx_tlv_get_tcp_chksum_9000,
hal_rx_get_rx_sequence_9000,
}; };
struct hal_hw_srng_config hw_srng_table_9000[] = { struct hal_hw_srng_config hw_srng_table_9000[] = {