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@@ -588,13 +588,6 @@ static int __power_off_iris2_controller(struct msm_vidc_core *core)
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rc = 0;
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rc = 0;
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}
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}
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- /* Turn off MVP MVS0 SRC clock */
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- rc = __disable_unprepare_clock_iris2(core, "video_cc_mvs0_clk_src");
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- if (rc) {
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- d_vpr_e("%s: disable unprepare video_cc_mvs0_clk_src failed\n", __func__);
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- rc = 0;
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- }
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-
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rc = call_venus_op(core, reset_ahb2axi_bridge, core);
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rc = call_venus_op(core, reset_ahb2axi_bridge, core);
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if (rc) {
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if (rc) {
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d_vpr_e("%s: reset ahb2axi bridge failed\n", __func__);
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d_vpr_e("%s: reset ahb2axi bridge failed\n", __func__);
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@@ -661,14 +654,8 @@ static int __power_on_iris2_controller(struct msm_vidc_core *core)
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if (rc)
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if (rc)
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goto fail_clk_controller;
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goto fail_clk_controller;
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- rc = __prepare_enable_clock_iris2(core, "video_cc_mvs0_clk_src");
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- if (rc)
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- goto fail_clk_src;
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-
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return 0;
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return 0;
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-fail_clk_src:
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- __disable_unprepare_clock_iris2(core, "core_clk");
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fail_clk_controller:
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fail_clk_controller:
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__disable_unprepare_clock_iris2(core, "gcc_video_axi0");
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__disable_unprepare_clock_iris2(core, "gcc_video_axi0");
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fail_clk_axi:
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fail_clk_axi:
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