disp: msm: sde: Move SPR CFG 5 programming to AHB

Partial update of SPR CFG 5 is showing intermittent odd
behavior. Move CFG 5 programming to AHB path to resolve
the issue.

Change-Id: I0719de9ea29ffe2f75c072053162133681a1b007
Signed-off-by: Christopher Braga <[email protected]>

msm/sde/sde_hw_reg_dma_v1_color_proc.c

@@ -5390,8 +5390,7 @@ int reg_dmav1_setup_spr_cfg5_params(struct sde_hw_dspp *ctx,
 		struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
 		struct sde_hw_reg_dma_ops *dma_ops)
 {
-	uint32_t reg_off, base_off, i;
-	uint32_t reg[1];
+	uint32_t i, reg[1];
 	int rc = 0;
 
 	if (!payload->cfg18_en) {
@@ -5424,14 +5423,8 @@ int reg_dmav1_setup_spr_cfg5_params(struct sde_hw_dspp *ctx,
 		reg[0] |= APPLY_MASK_AND_SHIFT(val, 2, 4 * i);
 	}
 
-	base_off = ctx->hw.blk_off + ctx->cap->sblk->spr.base;
-	reg_off = base_off + 0x7C;
-	REG_DMA_SETUP_OPS(*dma_write_cfg, reg_off, reg, sizeof(u32), REG_SINGLE_WRITE, 0, 0, 0);
-	rc = dma_ops->setup_payload(dma_write_cfg);
-	if (rc)
-		DRM_ERROR("write spr cfg18 failed ret %d\n", rc);
-	else
-		ctx->spr_cfg_18_default = reg[0];
+	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->spr.base + 0x7C, reg[0]);
+	ctx->spr_cfg_18_default = reg[0];
 
 	return rc;
 }
@@ -5903,7 +5896,7 @@ int reg_dmav1_setup_spr_pu_common(struct sde_hw_dspp *ctx, struct sde_hw_cp_cfg
 			return -EINVAL;
 		}
 
-		if ((roi_list->spr_roi[0].x2 - roi_list->spr_roi[0].x1) != hw_cfg->displayh) {
+		if ((roi_list->spr_roi[0].x2 - roi_list->spr_roi[0].x1) != hw_cfg->panel_width) {
 			DRM_ERROR("pu region not full width %d\n",
 					(roi_list->spr_roi[0].x2 - roi_list->spr_roi[0].x1));
 			return -EINVAL;
@@ -5975,12 +5968,10 @@ void reg_dmav1_setup_spr_pu_cfgv1(struct sde_hw_dspp *ctx, void *cfg)
 
 void reg_dmav1_setup_spr_pu_cfgv2(struct sde_hw_dspp *ctx, void *cfg)
 {
-	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
 	struct sde_hw_cp_cfg *hw_cfg = cfg;
 	struct sde_reg_dma_kickoff_cfg kick_off;
 	struct sde_hw_reg_dma_ops *dma_ops;
 	struct sde_reg_dma_buffer *buffer;
-	uint32_t reg_off, base_off;
 	struct msm_roi_list *roi_list = NULL;
 	int rc;
 
@@ -6011,20 +6002,10 @@ void reg_dmav1_setup_spr_pu_cfgv2(struct sde_hw_dspp *ctx, void *cfg)
 		if (roi_list && roi_list->spr_roi[0].y1 != 0)
 			reg &= 0xFFFFFFFC;
 
-		if (roi_list && roi_list->spr_roi[0].y2 != hw_cfg->displayv)
+		if (roi_list && roi_list->spr_roi[0].y2 != hw_cfg->panel_height)
 			reg &= 0xFFFFFFCF;
 
-		base_off = ctx->hw.blk_off + ctx->cap->sblk->spr.base;
-		reg_off = base_off + 0x7C;
-
-		REG_DMA_INIT_OPS(dma_write_cfg, MDSS, SPR_PU_CFG, buffer);
-		REG_DMA_SETUP_OPS(dma_write_cfg, reg_off, &reg, sizeof(u32),
-				REG_SINGLE_WRITE, 0, 0, 0);
-		rc = dma_ops->setup_payload(&dma_write_cfg);
-		if (rc) {
-			DRM_ERROR("SPR V2 PU failed ret %d\n", rc);
-			return;
-		}
+		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->spr.base + 0x7C, reg);
 	}
 
 	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,