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audio-lnx: Propagate changes from kernel for msm_sdw/hdmi

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Add snapshot for msm_sdw codec/hdmi codec drivers for SDM targets.
The code is migrated from msm-4.9 kernel at the below cutoff -

(8efe4a8d64f: "ARM: dts: msm: add rotator vbif memtype
		setting to sdm845")

This changes are done to migrate msm_sdw/hdmi codec drivers
to this new audio kernel techpack.

Change-Id: Ia807b87a7c67957512a6b38cc62ae9cb5223c8b2
Signed-off-by: Asish Bhattacharya <asishb@codeaurora.org>
This commit is contained in:
Asish Bhattacharya
2017-07-25 15:15:56 +05:30
committed by Martin Fick
parent 3d0e01d5be
commit 366f750416
9 changed files with 3565 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

562
sound/soc/codecs/msm_hdmi_codec_rx.c Normal file
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@@ -0,0 +1,562 @@
/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/err.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <linux/msm_ext_display.h>
#define MSM_EXT_DISP_PCM_RATES SNDRV_PCM_RATE_48000
#define AUD_EXT_DISP_ACK_DISCONNECT (AUDIO_ACK_CONNECT ^ AUDIO_ACK_CONNECT)
#define AUD_EXT_DISP_ACK_CONNECT (AUDIO_ACK_CONNECT)
#define AUD_EXT_DISP_ACK_ENABLE (AUDIO_ACK_SET_ENABLE | AUDIO_ACK_ENABLE)
static const char *const ext_disp_audio_type_text[] = {"None", "HDMI", "DP"};
static const char *const ext_disp_audio_ack_text[] = {"Disconnect", "Connect",
"Ack_Enable"};
static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_audio_type, ext_disp_audio_type_text);
static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_audio_ack_state,
ext_disp_audio_ack_text);
struct msm_ext_disp_audio_codec_rx_data {
struct platform_device *ext_disp_core_pdev;
struct msm_ext_disp_audio_codec_ops ext_disp_ops;
int cable_status;
};
static int msm_ext_disp_edid_ctl_info(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct msm_ext_disp_audio_codec_rx_data *codec_data;
struct msm_ext_disp_audio_edid_blk edid_blk;
int rc;
codec_data = snd_soc_codec_get_drvdata(codec);
if (!codec_data) {
dev_err(codec->dev, "%s: codec_data is NULL\n", __func__);
return -EINVAL;
}
if (!codec_data->ext_disp_ops.get_audio_edid_blk) {
dev_dbg(codec->dev, "%s: get_audio_edid_blk() is NULL\n",
__func__);
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = 0;
return 0;
}
rc = codec_data->ext_disp_ops.get_audio_edid_blk(
codec_data->ext_disp_core_pdev, &edid_blk);
if (rc >= 0) {
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = edid_blk.audio_data_blk_size +
edid_blk.spk_alloc_data_blk_size;
}
dev_dbg(codec->dev, "%s: count: %d\n", __func__, uinfo->count);
return rc;
}
static int msm_ext_disp_edid_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol) {
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct msm_ext_disp_audio_codec_rx_data *codec_data;
struct msm_ext_disp_audio_edid_blk edid_blk;
int rc;
codec_data = snd_soc_codec_get_drvdata(codec);
if (!codec_data || !codec_data->ext_disp_ops.get_audio_edid_blk) {
dev_err(codec->dev, "%s: codec_data or get_audio_edid_blk() is NULL\n",
__func__);
return -EINVAL;
}
rc = codec_data->ext_disp_ops.get_audio_edid_blk(
codec_data->ext_disp_core_pdev, &edid_blk);
if (rc >= 0) {
if (sizeof(ucontrol->value.bytes.data) <
(edid_blk.audio_data_blk_size +
edid_blk.spk_alloc_data_blk_size)) {
dev_err(codec->dev,
"%s: Not enough memory to copy EDID data\n",
__func__);
return -ENOMEM;
}
memcpy(ucontrol->value.bytes.data,
edid_blk.audio_data_blk,
edid_blk.audio_data_blk_size);
memcpy((ucontrol->value.bytes.data +
edid_blk.audio_data_blk_size),
edid_blk.spk_alloc_data_blk,
edid_blk.spk_alloc_data_blk_size);
dev_dbg(codec->dev, "%s: data_blk_size:%d, spk_alloc_data_blk_size:%d\n",
__func__, edid_blk.audio_data_blk_size,
edid_blk.spk_alloc_data_blk_size);
}
return rc;
}
static int msm_ext_disp_audio_type_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct msm_ext_disp_audio_codec_rx_data *codec_data;
enum msm_ext_disp_cable_state cable_state;
enum msm_ext_disp_type disp_type;
int rc;
codec_data = snd_soc_codec_get_drvdata(codec);
if (!codec_data ||
!codec_data->ext_disp_ops.get_audio_edid_blk ||
!codec_data->ext_disp_ops.get_intf_id) {
dev_err(codec->dev, "%s: codec_data, get_audio_edid_blk() or get_intf_id is NULL\n",
__func__);
return -EINVAL;
}
cable_state = codec_data->ext_disp_ops.cable_status(
codec_data->ext_disp_core_pdev, 1);
if (cable_state < 0) {
dev_err(codec->dev, "%s: Error retrieving cable state from ext_disp, err:%d\n",
__func__, cable_state);
rc = cable_state;
goto done;
}
codec_data->cable_status = cable_state;
if (cable_state == EXT_DISPLAY_CABLE_DISCONNECT) {
dev_err(codec->dev, "%s: Display cable disconnected\n",
__func__);
ucontrol->value.integer.value[0] = 0;
rc = 0;
goto done;
}
disp_type = codec_data->ext_disp_ops.get_intf_id(
codec_data->ext_disp_core_pdev);
if (disp_type >= 0) {
switch (disp_type) {
case EXT_DISPLAY_TYPE_DP:
ucontrol->value.integer.value[0] = 2;
rc = 0;
break;
case EXT_DISPLAY_TYPE_HDMI:
ucontrol->value.integer.value[0] = 1;
rc = 0;
break;
default:
rc = -EINVAL;
dev_err(codec->dev, "%s: Invalid disp_type:%d\n",
__func__, disp_type);
goto done;
}
dev_dbg(codec->dev, "%s: Display type: %d\n",
__func__, disp_type);
} else {
dev_err(codec->dev, "%s: Error retrieving disp_type from ext_disp, err:%d\n",
__func__, disp_type);
rc = disp_type;
}
done:
return rc;
}
static int msm_ext_disp_audio_ack_set(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
struct msm_ext_disp_audio_codec_rx_data *codec_data;
u32 ack_state = 0;
int rc;
codec_data = snd_soc_codec_get_drvdata(codec);
if (!codec_data ||
!codec_data->ext_disp_ops.acknowledge) {
dev_err(codec->dev,
"%s: codec_data or ops acknowledge() is NULL\n",
__func__);
rc = -EINVAL;
goto done;
}
switch (ucontrol->value.enumerated.item[0]) {
case 0:
ack_state = AUD_EXT_DISP_ACK_DISCONNECT;
break;
case 1:
ack_state = AUD_EXT_DISP_ACK_CONNECT;
break;
case 2:
ack_state = AUD_EXT_DISP_ACK_ENABLE;
break;
default:
rc = -EINVAL;
dev_err(codec->dev,
"%s: invalid value %d for mixer ctl\n",
__func__, ucontrol->value.enumerated.item[0]);
goto done;
}
dev_dbg(codec->dev, "%s: control %d, ack set value 0x%x\n",
__func__, ucontrol->value.enumerated.item[0], ack_state);
rc = codec_data->ext_disp_ops.acknowledge(
codec_data->ext_disp_core_pdev, ack_state);
if (rc < 0) {
dev_err(codec->dev, "%s: error from acknowledge(), err:%d\n",
__func__, rc);
}
done:
return rc;
}
static const struct snd_kcontrol_new msm_ext_disp_codec_rx_controls[] = {
{
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "HDMI EDID",
.info = msm_ext_disp_edid_ctl_info,
.get = msm_ext_disp_edid_get,
},
{
.access = SNDRV_CTL_ELEM_ACCESS_READ |
SNDRV_CTL_ELEM_ACCESS_VOLATILE,
.iface = SNDRV_CTL_ELEM_IFACE_PCM,
.name = "Display Port EDID",
.info = msm_ext_disp_edid_ctl_info,
.get = msm_ext_disp_edid_get,
},
SOC_ENUM_EXT("External Display Type", ext_disp_audio_type,
msm_ext_disp_audio_type_get, NULL),
SOC_ENUM_EXT("External Display Audio Ack", ext_disp_audio_ack_state,
NULL, msm_ext_disp_audio_ack_set),
};
static int msm_ext_disp_audio_codec_rx_dai_startup(
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int ret = 0;
struct msm_ext_disp_audio_codec_rx_data *codec_data =
dev_get_drvdata(dai->codec->dev);
if (!codec_data || !codec_data->ext_disp_ops.cable_status) {
dev_err(dai->dev, "%s() codec_data or cable_status is null\n",
__func__);
return -EINVAL;
}
codec_data->cable_status =
codec_data->ext_disp_ops.cable_status(
codec_data->ext_disp_core_pdev, 1);
if (codec_data->cable_status < 0) {
dev_err(dai->dev,
"%s() ext disp core is not ready (ret val = %d)\n",
__func__, codec_data->cable_status);
ret = codec_data->cable_status;
} else if (!codec_data->cable_status) {
dev_err(dai->dev,
"%s() ext disp cable is not connected (ret val = %d)\n",
__func__, codec_data->cable_status);
ret = -ENODEV;
}
return ret;
}
static int msm_ext_disp_audio_codec_rx_dai_hw_params(
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
u32 channel_allocation = 0;
u32 level_shift = 0; /* 0dB */
bool down_mix = 0;
u32 num_channels = params_channels(params);
int rc = 0;
struct msm_ext_disp_audio_setup_params audio_setup_params = {0};
struct msm_ext_disp_audio_codec_rx_data *codec_data =
dev_get_drvdata(dai->codec->dev);
if (!codec_data || !codec_data->ext_disp_ops.audio_info_setup) {
dev_err(dai->dev, "%s: codec_data or audio_info_setup is null\n",
__func__);
return -EINVAL;
}
if (codec_data->cable_status < 0) {
dev_err_ratelimited(dai->dev,
"%s() ext disp core is not ready (ret val = %d)\n",
__func__, codec_data->cable_status);
return codec_data->cable_status;
} else if (!codec_data->cable_status) {
dev_err_ratelimited(dai->dev,
"%s() ext disp cable is not connected (ret val = %d)\n",
__func__, codec_data->cable_status);
return -ENODEV;
}
/*refer to HDMI spec CEA-861-E: Table 28 Audio InfoFrame Data Byte 4*/
switch (num_channels) {
case 2:
channel_allocation = 0;
break;
case 3:
channel_allocation = 0x02;/*default to FL/FR/FC*/
audio_setup_params.sample_present = 0x3;
break;
case 4:
channel_allocation = 0x06;/*default to FL/FR/FC/RC*/
audio_setup_params.sample_present = 0x7;
break;
case 5:
channel_allocation = 0x0A;/*default to FL/FR/FC/RR/RL*/
audio_setup_params.sample_present = 0x7;
break;
case 6:
channel_allocation = 0x0B;
audio_setup_params.sample_present = 0x7;
break;
case 7:
channel_allocation = 0x12;/*default to FL/FR/FC/RL/RR/RRC/RLC*/
audio_setup_params.sample_present = 0xf;
break;
case 8:
channel_allocation = 0x13;
audio_setup_params.sample_present = 0xf;
break;
default:
dev_err(dai->dev, "invalid Channels = %u\n", num_channels);
return -EINVAL;
}
dev_dbg(dai->dev,
"%s() num_ch %u samplerate %u channel_allocation = %u\n",
__func__, num_channels, params_rate(params),
channel_allocation);
audio_setup_params.sample_rate_hz = params_rate(params);
audio_setup_params.num_of_channels = num_channels;
audio_setup_params.channel_allocation = channel_allocation;
audio_setup_params.level_shift = level_shift;
audio_setup_params.down_mix = down_mix;
rc = codec_data->ext_disp_ops.audio_info_setup(
codec_data->ext_disp_core_pdev, &audio_setup_params);
if (rc < 0) {
dev_err_ratelimited(dai->dev,
"%s() ext disp core is not ready, rc: %d\n",
__func__, rc);
}
return rc;
}
static void msm_ext_disp_audio_codec_rx_dai_shutdown(
struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
int rc;
struct msm_ext_disp_audio_codec_rx_data *codec_data =
dev_get_drvdata(dai->codec->dev);
if (!codec_data || !codec_data->ext_disp_ops.teardown_done ||
!codec_data->ext_disp_ops.cable_status) {
dev_err(dai->dev, "%s: codec data or teardown_done or cable_status is null\n",
__func__);
return;
}
rc = codec_data->ext_disp_ops.cable_status(
codec_data->ext_disp_core_pdev, 0);
if (rc < 0) {
dev_err(dai->dev,
"%s: ext disp core had problems releasing audio flag\n",
__func__);
}
codec_data->ext_disp_ops.teardown_done(
codec_data->ext_disp_core_pdev);
}
static int msm_ext_disp_audio_codec_rx_probe(struct snd_soc_codec *codec)
{
struct msm_ext_disp_audio_codec_rx_data *codec_data;
struct device_node *of_node_parent = NULL;
codec_data = kzalloc(sizeof(struct msm_ext_disp_audio_codec_rx_data),
GFP_KERNEL);
if (!codec_data) {
dev_err(codec->dev, "%s(): fail to allocate dai data\n",
__func__);
return -ENOMEM;
}
of_node_parent = of_get_parent(codec->dev->of_node);
if (!of_node_parent) {
dev_err(codec->dev, "%s(): Parent device tree node not found\n",
__func__);
kfree(codec_data);
return -ENODEV;
}
codec_data->ext_disp_core_pdev = of_find_device_by_node(of_node_parent);
if (!codec_data->ext_disp_core_pdev) {
dev_err(codec->dev, "%s(): can't get parent pdev\n", __func__);
kfree(codec_data);
return -ENODEV;
}
if (msm_ext_disp_register_audio_codec(codec_data->ext_disp_core_pdev,
&codec_data->ext_disp_ops)) {
dev_err(codec->dev, "%s(): can't register with ext disp core",
__func__);
kfree(codec_data);
return -ENODEV;
}
dev_set_drvdata(codec->dev, codec_data);
dev_dbg(codec->dev, "%s(): registered %s with ext disp core\n",
__func__, codec->component.name);
return 0;
}
static int msm_ext_disp_audio_codec_rx_remove(struct snd_soc_codec *codec)
{
struct msm_ext_disp_audio_codec_rx_data *codec_data;
codec_data = dev_get_drvdata(codec->dev);
kfree(codec_data);
return 0;
}
static struct snd_soc_dai_ops msm_ext_disp_audio_codec_rx_dai_ops = {
.startup = msm_ext_disp_audio_codec_rx_dai_startup,
.hw_params = msm_ext_disp_audio_codec_rx_dai_hw_params,
.shutdown = msm_ext_disp_audio_codec_rx_dai_shutdown
};
static struct snd_soc_dai_driver msm_ext_disp_audio_codec_rx_dais[] = {
{
.name = "msm_hdmi_audio_codec_rx_dai",
.playback = {
.stream_name = "HDMI Playback",
.channels_min = 1,
.channels_max = 8,
.rate_min = 48000,
.rate_max = 48000,
.rates = MSM_EXT_DISP_PCM_RATES,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &msm_ext_disp_audio_codec_rx_dai_ops,
},
{
.name = "msm_dp_audio_codec_rx_dai",
.playback = {
.stream_name = "Display Port Playback",
.channels_min = 1,
.channels_max = 8,
.rate_min = 48000,
.rate_max = 192000,
.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &msm_ext_disp_audio_codec_rx_dai_ops,
},
};
static struct snd_soc_codec_driver msm_ext_disp_audio_codec_rx_soc_driver = {
.probe = msm_ext_disp_audio_codec_rx_probe,
.remove = msm_ext_disp_audio_codec_rx_remove,
.component_driver = {
.controls = msm_ext_disp_codec_rx_controls,
.num_controls = ARRAY_SIZE(msm_ext_disp_codec_rx_controls),
},
};
static int msm_ext_disp_audio_codec_rx_plat_probe(
struct platform_device *pdev)
{
dev_dbg(&pdev->dev, "%s(): dev name %s\n", __func__,
dev_name(&pdev->dev));
return snd_soc_register_codec(&pdev->dev,
&msm_ext_disp_audio_codec_rx_soc_driver,
msm_ext_disp_audio_codec_rx_dais,
ARRAY_SIZE(msm_ext_disp_audio_codec_rx_dais));
}
static int msm_ext_disp_audio_codec_rx_plat_remove(
struct platform_device *pdev)
{
snd_soc_unregister_codec(&pdev->dev);
return 0;
}
static const struct of_device_id msm_ext_disp_audio_codec_rx_dt_match[] = {
{ .compatible = "qcom,msm-ext-disp-audio-codec-rx", },
{}
};
MODULE_DEVICE_TABLE(of, msm_ext_disp_audio_codec_rx_dt_match);
static struct platform_driver msm_ext_disp_audio_codec_rx_driver = {
.driver = {
.name = "msm-ext-disp-audio-codec-rx",
.owner = THIS_MODULE,
.of_match_table = msm_ext_disp_audio_codec_rx_dt_match,
},
.probe = msm_ext_disp_audio_codec_rx_plat_probe,
.remove = msm_ext_disp_audio_codec_rx_plat_remove,
};
static int __init msm_ext_disp_audio_codec_rx_init(void)
{
int rc;
rc = platform_driver_register(&msm_ext_disp_audio_codec_rx_driver);
if (rc) {
pr_err("%s: failed to register ext disp codec driver err:%d\n",
__func__, rc);
}
return rc;
}
module_init(msm_ext_disp_audio_codec_rx_init);
static void __exit msm_ext_disp_audio_codec_rx_exit(void)
{
platform_driver_unregister(&msm_ext_disp_audio_codec_rx_driver);
}
module_exit(msm_ext_disp_audio_codec_rx_exit);
MODULE_DESCRIPTION("MSM External Display Audio CODEC Driver");
MODULE_LICENSE("GPL v2");

6
sound/soc/codecs/msm_sdw/Kconfig Normal file
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@@ -0,0 +1,6 @@
config SND_SOC_MSM_SDW
tristate "MSM Internal soundwire codec"
help
MSM-based soundwire codec core driver
supported along with internal digital
codec core.

3
sound/soc/codecs/msm_sdw/Makefile Normal file
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@@ -0,0 +1,3 @@
snd-soc-msm-sdw-objs := msm_sdw_cdc.o msm_sdw_regmap.o msm-sdw-tables.o msm_sdw_cdc_utils.o
obj-$(CONFIG_SND_SOC_MSM_SDW) += snd-soc-msm-sdw.o
ccflags-y += -I$(srctree)/sound/soc/msm

319
sound/soc/codecs/msm_sdw/msm-sdw-tables.c Normal file
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@@ -0,0 +1,319 @@
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/types.h>
#include "msm_sdw.h"
const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER] = {
[MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 0xa,
[MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 0xa,
[MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 0xa,
[MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 0xa,
[MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 0xa,
[MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 0xa,
[MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 0xa,
[MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 0xa,
[MSM_SDW_COMPANDER7_CTL0] = 0xb,
[MSM_SDW_COMPANDER7_CTL1] = 0xb,
[MSM_SDW_COMPANDER7_CTL2] = 0xb,
[MSM_SDW_COMPANDER7_CTL3] = 0xb,
[MSM_SDW_COMPANDER7_CTL4] = 0xb,
[MSM_SDW_COMPANDER7_CTL5] = 0xb,
[MSM_SDW_COMPANDER7_CTL6] = 0xb,
[MSM_SDW_COMPANDER7_CTL7] = 0xb,
[MSM_SDW_COMPANDER8_CTL0] = 0xb,
[MSM_SDW_COMPANDER8_CTL1] = 0xb,
[MSM_SDW_COMPANDER8_CTL2] = 0xb,
[MSM_SDW_COMPANDER8_CTL3] = 0xb,
[MSM_SDW_COMPANDER8_CTL4] = 0xb,
[MSM_SDW_COMPANDER8_CTL5] = 0xb,
[MSM_SDW_COMPANDER8_CTL6] = 0xb,
[MSM_SDW_COMPANDER8_CTL7] = 0xb,
[MSM_SDW_RX7_RX_PATH_CTL] = 0xb,
[MSM_SDW_RX7_RX_PATH_CFG0] = 0xb,
[MSM_SDW_RX7_RX_PATH_CFG1] = 0xb,
[MSM_SDW_RX7_RX_PATH_CFG2] = 0xb,
[MSM_SDW_RX7_RX_VOL_CTL] = 0xb,
[MSM_SDW_RX7_RX_PATH_MIX_CTL] = 0xb,
[MSM_SDW_RX7_RX_PATH_MIX_CFG] = 0xb,
[MSM_SDW_RX7_RX_VOL_MIX_CTL] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC0] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC1] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC2] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC3] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC5] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC6] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC7] = 0xb,
[MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 0xb,
[MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 0xb,
[MSM_SDW_RX8_RX_PATH_CTL] = 0xb,
[MSM_SDW_RX8_RX_PATH_CFG0] = 0xb,
[MSM_SDW_RX8_RX_PATH_CFG1] = 0xb,
[MSM_SDW_RX8_RX_PATH_CFG2] = 0xb,
[MSM_SDW_RX8_RX_VOL_CTL] = 0xb,
[MSM_SDW_RX8_RX_PATH_MIX_CTL] = 0xb,
[MSM_SDW_RX8_RX_PATH_MIX_CFG] = 0xb,
[MSM_SDW_RX8_RX_VOL_MIX_CTL] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC0] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC1] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC2] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC3] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC5] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC6] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC7] = 0xb,
[MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 0xb,
[MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 0xb,
[MSM_SDW_BOOST0_BOOST_PATH_CTL] = 0xc,
[MSM_SDW_BOOST0_BOOST_CTL] = 0xc,
[MSM_SDW_BOOST0_BOOST_CFG1] = 0xc,
[MSM_SDW_BOOST0_BOOST_CFG2] = 0xc,
[MSM_SDW_BOOST1_BOOST_PATH_CTL] = 0xc,
[MSM_SDW_BOOST1_BOOST_CTL] = 0xc,
[MSM_SDW_BOOST1_BOOST_CFG1] = 0xc,
[MSM_SDW_BOOST1_BOOST_CFG2] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_DATA_0] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_DATA_1] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_DATA_2] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_DATA_3] = 0xc,
[MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 0xc,
[MSM_SDW_AHB_BRIDGE_ACCESS_STATUS] = 0xc,
[MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 0xd,
[MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 0xd,
[MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 0xd,
[MSM_SDW_TOP_TOP_CFG0] = 0xd,
[MSM_SDW_TOP_TOP_CFG1] = 0xd,
[MSM_SDW_TOP_RX_I2S_CTL] = 0xd,
[MSM_SDW_TOP_TX_I2S_CTL] = 0xd,
[MSM_SDW_TOP_I2S_CLK] = 0xd,
[MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 0xd,
[MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 0xd,
[MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 0xd,
[MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 0xd,
[MSM_SDW_TOP_FREQ_MCLK] = 0xd,
[MSM_SDW_TOP_DEBUG_BUS_SEL] = 0xd,
[MSM_SDW_TOP_DEBUG_EN] = 0xd,
[MSM_SDW_TOP_I2S_RESET] = 0xd,
[MSM_SDW_TOP_BLOCKS_RESET] = 0xd,
};
const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER] = {
[MSM_SDW_PAGE_REGISTER] = 1,
[MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_COMPANDER7_CTL0] = 1,
[MSM_SDW_COMPANDER7_CTL1] = 1,
[MSM_SDW_COMPANDER7_CTL2] = 1,
[MSM_SDW_COMPANDER7_CTL3] = 1,
[MSM_SDW_COMPANDER7_CTL4] = 1,
[MSM_SDW_COMPANDER7_CTL5] = 1,
[MSM_SDW_COMPANDER7_CTL6] = 1,
[MSM_SDW_COMPANDER7_CTL7] = 1,
[MSM_SDW_COMPANDER8_CTL0] = 1,
[MSM_SDW_COMPANDER8_CTL1] = 1,
[MSM_SDW_COMPANDER8_CTL2] = 1,
[MSM_SDW_COMPANDER8_CTL3] = 1,
[MSM_SDW_COMPANDER8_CTL4] = 1,
[MSM_SDW_COMPANDER8_CTL5] = 1,
[MSM_SDW_COMPANDER8_CTL6] = 1,
[MSM_SDW_COMPANDER8_CTL7] = 1,
[MSM_SDW_RX7_RX_PATH_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_CFG0] = 1,
[MSM_SDW_RX7_RX_PATH_CFG1] = 1,
[MSM_SDW_RX7_RX_PATH_CFG2] = 1,
[MSM_SDW_RX7_RX_VOL_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_CFG] = 1,
[MSM_SDW_RX7_RX_VOL_MIX_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_SEC0] = 1,
[MSM_SDW_RX7_RX_PATH_SEC1] = 1,
[MSM_SDW_RX7_RX_PATH_SEC2] = 1,
[MSM_SDW_RX7_RX_PATH_SEC3] = 1,
[MSM_SDW_RX7_RX_PATH_SEC5] = 1,
[MSM_SDW_RX7_RX_PATH_SEC6] = 1,
[MSM_SDW_RX7_RX_PATH_SEC7] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 1,
[MSM_SDW_RX8_RX_PATH_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_CFG0] = 1,
[MSM_SDW_RX8_RX_PATH_CFG1] = 1,
[MSM_SDW_RX8_RX_PATH_CFG2] = 1,
[MSM_SDW_RX8_RX_VOL_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_CFG] = 1,
[MSM_SDW_RX8_RX_VOL_MIX_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_SEC0] = 1,
[MSM_SDW_RX8_RX_PATH_SEC1] = 1,
[MSM_SDW_RX8_RX_PATH_SEC2] = 1,
[MSM_SDW_RX8_RX_PATH_SEC3] = 1,
[MSM_SDW_RX8_RX_PATH_SEC5] = 1,
[MSM_SDW_RX8_RX_PATH_SEC6] = 1,
[MSM_SDW_RX8_RX_PATH_SEC7] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 1,
[MSM_SDW_BOOST0_BOOST_PATH_CTL] = 1,
[MSM_SDW_BOOST0_BOOST_CTL] = 1,
[MSM_SDW_BOOST0_BOOST_CFG1] = 1,
[MSM_SDW_BOOST0_BOOST_CFG2] = 1,
[MSM_SDW_BOOST1_BOOST_PATH_CTL] = 1,
[MSM_SDW_BOOST1_BOOST_CTL] = 1,
[MSM_SDW_BOOST1_BOOST_CFG1] = 1,
[MSM_SDW_BOOST1_BOOST_CFG2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 1,
[MSM_SDW_AHB_BRIDGE_RD_DATA_0] = 1,
[MSM_SDW_AHB_BRIDGE_RD_DATA_1] = 1,
[MSM_SDW_AHB_BRIDGE_RD_DATA_2] = 1,
[MSM_SDW_AHB_BRIDGE_RD_DATA_3] = 1,
[MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 1,
[MSM_SDW_AHB_BRIDGE_ACCESS_STATUS] = 1,
[MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 1,
[MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 1,
[MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 1,
[MSM_SDW_TOP_TOP_CFG0] = 1,
[MSM_SDW_TOP_TOP_CFG1] = 1,
[MSM_SDW_TOP_RX_I2S_CTL] = 1,
[MSM_SDW_TOP_TX_I2S_CTL] = 1,
[MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 1,
[MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 1,
[MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 1,
[MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 1,
[MSM_SDW_TOP_FREQ_MCLK] = 1,
[MSM_SDW_TOP_DEBUG_BUS_SEL] = 1,
[MSM_SDW_TOP_DEBUG_EN] = 1,
[MSM_SDW_TOP_I2S_RESET] = 1,
[MSM_SDW_TOP_BLOCKS_RESET] = 1,
};
const u8 msm_sdw_reg_writeable[MSM_SDW_MAX_REGISTER] = {
[MSM_SDW_PAGE_REGISTER] = 1,
[MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_COMPANDER7_CTL0] = 1,
[MSM_SDW_COMPANDER7_CTL1] = 1,
[MSM_SDW_COMPANDER7_CTL2] = 1,
[MSM_SDW_COMPANDER7_CTL3] = 1,
[MSM_SDW_COMPANDER7_CTL4] = 1,
[MSM_SDW_COMPANDER7_CTL5] = 1,
[MSM_SDW_COMPANDER7_CTL7] = 1,
[MSM_SDW_COMPANDER8_CTL0] = 1,
[MSM_SDW_COMPANDER8_CTL1] = 1,
[MSM_SDW_COMPANDER8_CTL2] = 1,
[MSM_SDW_COMPANDER8_CTL3] = 1,
[MSM_SDW_COMPANDER8_CTL4] = 1,
[MSM_SDW_COMPANDER8_CTL5] = 1,
[MSM_SDW_COMPANDER8_CTL7] = 1,
[MSM_SDW_RX7_RX_PATH_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_CFG0] = 1,
[MSM_SDW_RX7_RX_PATH_CFG1] = 1,
[MSM_SDW_RX7_RX_PATH_CFG2] = 1,
[MSM_SDW_RX7_RX_VOL_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_CFG] = 1,
[MSM_SDW_RX7_RX_VOL_MIX_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_SEC0] = 1,
[MSM_SDW_RX7_RX_PATH_SEC1] = 1,
[MSM_SDW_RX7_RX_PATH_SEC2] = 1,
[MSM_SDW_RX7_RX_PATH_SEC3] = 1,
[MSM_SDW_RX7_RX_PATH_SEC5] = 1,
[MSM_SDW_RX7_RX_PATH_SEC6] = 1,
[MSM_SDW_RX7_RX_PATH_SEC7] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 1,
[MSM_SDW_RX8_RX_PATH_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_CFG0] = 1,
[MSM_SDW_RX8_RX_PATH_CFG1] = 1,
[MSM_SDW_RX8_RX_PATH_CFG2] = 1,
[MSM_SDW_RX8_RX_VOL_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_CFG] = 1,
[MSM_SDW_RX8_RX_VOL_MIX_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_SEC0] = 1,
[MSM_SDW_RX8_RX_PATH_SEC1] = 1,
[MSM_SDW_RX8_RX_PATH_SEC2] = 1,
[MSM_SDW_RX8_RX_PATH_SEC3] = 1,
[MSM_SDW_RX8_RX_PATH_SEC5] = 1,
[MSM_SDW_RX8_RX_PATH_SEC6] = 1,
[MSM_SDW_RX8_RX_PATH_SEC7] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 1,
[MSM_SDW_BOOST0_BOOST_PATH_CTL] = 1,
[MSM_SDW_BOOST0_BOOST_CTL] = 1,
[MSM_SDW_BOOST0_BOOST_CFG1] = 1,
[MSM_SDW_BOOST0_BOOST_CFG2] = 1,
[MSM_SDW_BOOST1_BOOST_PATH_CTL] = 1,
[MSM_SDW_BOOST1_BOOST_CTL] = 1,
[MSM_SDW_BOOST1_BOOST_CFG1] = 1,
[MSM_SDW_BOOST1_BOOST_CFG2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 1,
[MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 1,
[MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 1,
[MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 1,
[MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 1,
[MSM_SDW_TOP_TOP_CFG0] = 1,
[MSM_SDW_TOP_TOP_CFG1] = 1,
[MSM_SDW_TOP_RX_I2S_CTL] = 1,
[MSM_SDW_TOP_TX_I2S_CTL] = 1,
[MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 1,
[MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 1,
[MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 1,
[MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 1,
[MSM_SDW_TOP_FREQ_MCLK] = 1,
[MSM_SDW_TOP_DEBUG_BUS_SEL] = 1,
[MSM_SDW_TOP_DEBUG_EN] = 1,
[MSM_SDW_TOP_I2S_RESET] = 1,
[MSM_SDW_TOP_BLOCKS_RESET] = 1,
};

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sound/soc/codecs/msm_sdw/msm_sdw.h Normal file
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/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MSM_SDW_H
#define MSM_SDW_H
#include <sound/soc.h>
#include <sound/q6afe-v2.h>
#include "msm_sdw_registers.h"
#define MSM_SDW_MAX_REGISTER 0x400
extern const struct regmap_config msm_sdw_regmap_config;
extern const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER];
extern const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER];
extern const u8 msm_sdw_reg_writeable[MSM_SDW_MAX_REGISTER];
enum {
MSM_SDW_RX4 = 0,
MSM_SDW_RX5,
MSM_SDW_RX_MAX,
};
enum {
MSM_SDW_TX0 = 0,
MSM_SDW_TX1,
MSM_SDW_TX_MAX,
};
enum {
COMP1, /* SPK_L */
COMP2, /* SPK_R */
COMP_MAX
};
/*
* Structure used to update codec
* register defaults after reset
*/
struct msm_sdw_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
/*
* Selects compander and smart boost settings
* for a given speaker mode
*/
enum {
SPKR_MODE_DEFAULT,
SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
};
/* Rx path gain offsets */
enum {
RX_GAIN_OFFSET_M1P5_DB,
RX_GAIN_OFFSET_0_DB,
};
struct msm_sdw_reg_val {
unsigned short reg; /* register address */
u8 *buf; /* buffer to be written to reg. addr */
int bytes; /* number of bytes to be written */
};
/* Hold instance to soundwire platform device */
struct msm_sdw_ctrl_data {
struct platform_device *sdw_pdev;
};
struct wcd_sdw_ctrl_platform_data {
void *handle; /* holds codec private data */
int (*read)(void *handle, int reg);
int (*write)(void *handle, int reg, int val);
int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
int (*clk)(void *handle, bool enable);
int (*handle_irq)(void *handle,
irqreturn_t (*swrm_irq_handler)(int irq,
void *data),
void *swrm_handle,
int action);
};
struct msm_sdw_priv {
struct device *dev;
struct mutex io_lock;
int (*read_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
int bytes, void *dest);
int (*write_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
int bytes, void *src);
int (*multi_reg_write)(struct msm_sdw_priv *msm_sdw, const void *data,
size_t count);
struct snd_soc_codec *codec;
struct device_node *sdw_gpio_p; /* used by pinctrl API */
/* SoundWire data structure */
struct msm_sdw_ctrl_data *sdw_ctrl_data;
int nr;
/* compander */
int comp_enabled[COMP_MAX];
int ear_spkr_gain;
/* to track the status */
unsigned long status_mask;
struct work_struct msm_sdw_add_child_devices_work;
struct wcd_sdw_ctrl_platform_data sdw_plat_data;
unsigned int vi_feed_value;
struct mutex sdw_read_lock;
struct mutex sdw_write_lock;
struct mutex sdw_clk_lock;
int sdw_clk_users;
int sdw_mclk_users;
int sdw_irq;
int int_mclk1_rsc_ref;
bool int_mclk1_enabled;
bool sdw_npl_clk_enabled;
struct mutex cdc_int_mclk1_mutex;
struct mutex sdw_npl_clk_mutex;
struct delayed_work disable_int_mclk1_work;
struct afe_clk_set sdw_cdc_core_clk;
struct afe_clk_set sdw_npl_clk;
struct notifier_block service_nb;
int (*sdw_cdc_gpio_fn)(bool enable, struct snd_soc_codec *codec);
bool dev_up;
int spkr_gain_offset;
int spkr_mode;
struct mutex codec_mutex;
int rx_4_count;
int rx_5_count;
u32 mclk_rate;
struct regmap *regmap;
bool prev_pg_valid;
u8 prev_pg;
u32 sdw_base_addr;
char __iomem *sdw_base;
u32 version;
/* Entry for version info */
struct snd_info_entry *entry;
struct snd_info_entry *version_entry;
};
extern int msm_sdw_set_spkr_mode(struct snd_soc_codec *codec, int mode);
extern int msm_sdw_set_spkr_gain_offset(struct snd_soc_codec *codec,
int offset);
extern void msm_sdw_gpio_cb(
int (*sdw_cdc_gpio_fn)(bool enable, struct snd_soc_codec *codec),
struct snd_soc_codec *codec);
extern struct regmap *msm_sdw_regmap_init(struct device *dev,
const struct regmap_config *config);
extern int msm_sdw_codec_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_codec *codec);
#endif

2007
sound/soc/codecs/msm_sdw/msm_sdw_cdc.c Normal file
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sound/soc/codecs/msm_sdw/msm_sdw_cdc_utils.c Normal file
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/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/regmap.h>
#include "msm_sdw.h"
#define REG_BYTES 2
#define VAL_BYTES 1
/*
* Page Register Address that APP Proc uses to
* access WCD9335 Codec registers is identified
* as 0x00
*/
#define PAGE_REG_ADDR 0x00
/*
* msm_sdw_page_write:
* Retrieve page number from register and
* write that page number to the page address.
* Called under io_lock acquisition.
*
* @msm_sdw: pointer to msm_sdw
* @reg: Register address from which page number is retrieved
*
* Returns 0 for success and negative error code for failure.
*/
int msm_sdw_page_write(struct msm_sdw_priv *msm_sdw, unsigned short reg)
{
int ret = 0;
u8 pg_num, prev_pg_num;
pg_num = msm_sdw_page_map[reg];
if (msm_sdw->prev_pg_valid) {
prev_pg_num = msm_sdw->prev_pg;
if (prev_pg_num != pg_num) {
ret = msm_sdw->write_dev(msm_sdw, PAGE_REG_ADDR, 1,
(void *) &pg_num);
if (ret < 0) {
dev_err(msm_sdw->dev,
"page write error, pg_num: 0x%x\n",
pg_num);
} else {
msm_sdw->prev_pg = pg_num;
dev_dbg(msm_sdw->dev,
"%s: Page 0x%x Write to 0x00\n",
__func__, pg_num);
}
}
} else {
ret = msm_sdw->write_dev(msm_sdw, PAGE_REG_ADDR, 1,
(void *) &pg_num);
if (ret < 0) {
dev_err(msm_sdw->dev,
"page write error, pg_num: 0x%x\n", pg_num);
} else {
msm_sdw->prev_pg = pg_num;
msm_sdw->prev_pg_valid = true;
dev_dbg(msm_sdw->dev, "%s: Page 0x%x Write to 0x00\n",
__func__, pg_num);
}
}
return ret;
}
EXPORT_SYMBOL(msm_sdw_page_write);
static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct device *dev = context;
struct msm_sdw_priv *msm_sdw = dev_get_drvdata(dev);
unsigned short c_reg;
int ret, i;
if (!msm_sdw) {
dev_err(dev, "%s: msm_sdw is NULL\n", __func__);
return -EINVAL;
}
if (!reg || !val) {
dev_err(dev, "%s: reg or val is NULL\n", __func__);
return -EINVAL;
}
if (reg_size != REG_BYTES) {
dev_err(dev, "%s: register size %zd bytes, not supported\n",
__func__, reg_size);
return -EINVAL;
}
if (!msm_sdw->dev_up) {
dev_dbg_ratelimited(dev, "%s: No read allowed. dev_up = %d\n",
__func__, msm_sdw->dev_up);
return 0;
}
mutex_lock(&msm_sdw->io_lock);
c_reg = *(u16 *)reg;
ret = msm_sdw_page_write(msm_sdw, c_reg);
if (ret)
goto err;
ret = msm_sdw->read_dev(msm_sdw, c_reg, val_size, val);
if (ret < 0)
dev_err(dev, "%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
__func__, ret, c_reg, val_size);
else {
for (i = 0; i < val_size; i++)
dev_dbg(dev, "%s: Read 0x%02x from 0x%x\n",
__func__, ((u8 *)val)[i], c_reg + i);
}
err:
mutex_unlock(&msm_sdw->io_lock);
return ret;
}
static int regmap_bus_gather_write(void *context,
const void *reg, size_t reg_size,
const void *val, size_t val_size)
{
struct device *dev = context;
struct msm_sdw_priv *msm_sdw = dev_get_drvdata(dev);
unsigned short c_reg;
int ret, i;
if (!msm_sdw) {
dev_err(dev, "%s: msm_sdw is NULL\n", __func__);
return -EINVAL;
}
if (!reg || !val) {
dev_err(dev, "%s: reg or val is NULL\n", __func__);
return -EINVAL;
}
if (reg_size != REG_BYTES) {
dev_err(dev, "%s: register size %zd bytes, not supported\n",
__func__, reg_size);
return -EINVAL;
}
if (!msm_sdw->dev_up) {
dev_dbg_ratelimited(dev, "%s: No write allowed. dev_up = %d\n",
__func__, msm_sdw->dev_up);
return 0;
}
mutex_lock(&msm_sdw->io_lock);
c_reg = *(u16 *)reg;
ret = msm_sdw_page_write(msm_sdw, c_reg);
if (ret)
goto err;
for (i = 0; i < val_size; i++)
dev_dbg(dev, "Write %02x to 0x%x\n", ((u8 *)val)[i],
c_reg + i*4);
ret = msm_sdw->write_dev(msm_sdw, c_reg, val_size, (void *) val);
if (ret < 0)
dev_err(dev,
"%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
__func__, ret, c_reg, val_size);
err:
mutex_unlock(&msm_sdw->io_lock);
return ret;
}
static int regmap_bus_write(void *context, const void *data, size_t count)
{
struct device *dev = context;
struct msm_sdw_priv *msm_sdw = dev_get_drvdata(dev);
if (!msm_sdw)
return -EINVAL;
WARN_ON(count < REG_BYTES);
return regmap_bus_gather_write(context, data, REG_BYTES,
data + REG_BYTES,
count - REG_BYTES);
}
static struct regmap_bus regmap_bus_config = {
.write = regmap_bus_write,
.gather_write = regmap_bus_gather_write,
.read = regmap_bus_read,
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
};
/*
* msm_sdw_regmap_init:
* Initialize msm_sdw register map
*
* @dev: pointer to wcd device
* @config: pointer to register map config
*
* Returns pointer to regmap structure for success
* or NULL in case of failure.
*/
struct regmap *msm_sdw_regmap_init(struct device *dev,
const struct regmap_config *config)
{
return devm_regmap_init(dev, &regmap_bus_config, dev, config);
}
EXPORT_SYMBOL(msm_sdw_regmap_init);

126
sound/soc/codecs/msm_sdw/msm_sdw_registers.h Normal file
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/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MSM_SDW_REGISTERS_H
#define MSM_SDW_REGISTERS_H
#define MSM_SDW_PAGE_REGISTER 0x0000
/* Page-A Registers */
#define MSM_SDW_TX9_SPKR_PROT_PATH_CTL 0x0308
#define MSM_SDW_TX9_SPKR_PROT_PATH_CFG0 0x030c
#define MSM_SDW_TX10_SPKR_PROT_PATH_CTL 0x0318
#define MSM_SDW_TX10_SPKR_PROT_PATH_CFG0 0x031c
#define MSM_SDW_TX11_SPKR_PROT_PATH_CTL 0x0328
#define MSM_SDW_TX11_SPKR_PROT_PATH_CFG0 0x032c
#define MSM_SDW_TX12_SPKR_PROT_PATH_CTL 0x0338
#define MSM_SDW_TX12_SPKR_PROT_PATH_CFG0 0x033c
/* Page-B Registers */
#define MSM_SDW_COMPANDER7_CTL0 0x0024
#define MSM_SDW_COMPANDER7_CTL1 0x0028
#define MSM_SDW_COMPANDER7_CTL2 0x002c
#define MSM_SDW_COMPANDER7_CTL3 0x0030
#define MSM_SDW_COMPANDER7_CTL4 0x0034
#define MSM_SDW_COMPANDER7_CTL5 0x0038
#define MSM_SDW_COMPANDER7_CTL6 0x003c
#define MSM_SDW_COMPANDER7_CTL7 0x0040
#define MSM_SDW_COMPANDER8_CTL0 0x0044
#define MSM_SDW_COMPANDER8_CTL1 0x0048
#define MSM_SDW_COMPANDER8_CTL2 0x004c
#define MSM_SDW_COMPANDER8_CTL3 0x0050
#define MSM_SDW_COMPANDER8_CTL4 0x0054
#define MSM_SDW_COMPANDER8_CTL5 0x0058
#define MSM_SDW_COMPANDER8_CTL6 0x005c
#define MSM_SDW_COMPANDER8_CTL7 0x0060
#define MSM_SDW_RX7_RX_PATH_CTL 0x01a4
#define MSM_SDW_RX7_RX_PATH_CFG0 0x01a8
#define MSM_SDW_RX7_RX_PATH_CFG1 0x01ac
#define MSM_SDW_RX7_RX_PATH_CFG2 0x01b0
#define MSM_SDW_RX7_RX_VOL_CTL 0x01b4
#define MSM_SDW_RX7_RX_PATH_MIX_CTL 0x01b8
#define MSM_SDW_RX7_RX_PATH_MIX_CFG 0x01bc
#define MSM_SDW_RX7_RX_VOL_MIX_CTL 0x01c0
#define MSM_SDW_RX7_RX_PATH_SEC0 0x01c4
#define MSM_SDW_RX7_RX_PATH_SEC1 0x01c8
#define MSM_SDW_RX7_RX_PATH_SEC2 0x01cc
#define MSM_SDW_RX7_RX_PATH_SEC3 0x01d0
#define MSM_SDW_RX7_RX_PATH_SEC5 0x01d8
#define MSM_SDW_RX7_RX_PATH_SEC6 0x01dc
#define MSM_SDW_RX7_RX_PATH_SEC7 0x01e0
#define MSM_SDW_RX7_RX_PATH_MIX_SEC0 0x01e4
#define MSM_SDW_RX7_RX_PATH_MIX_SEC1 0x01e8
#define MSM_SDW_RX8_RX_PATH_CTL 0x0384
#define MSM_SDW_RX8_RX_PATH_CFG0 0x0388
#define MSM_SDW_RX8_RX_PATH_CFG1 0x038c
#define MSM_SDW_RX8_RX_PATH_CFG2 0x0390
#define MSM_SDW_RX8_RX_VOL_CTL 0x0394
#define MSM_SDW_RX8_RX_PATH_MIX_CTL 0x0398
#define MSM_SDW_RX8_RX_PATH_MIX_CFG 0x039c
#define MSM_SDW_RX8_RX_VOL_MIX_CTL 0x03a0
#define MSM_SDW_RX8_RX_PATH_SEC0 0x03a4
#define MSM_SDW_RX8_RX_PATH_SEC1 0x03a8
#define MSM_SDW_RX8_RX_PATH_SEC2 0x03ac
#define MSM_SDW_RX8_RX_PATH_SEC3 0x03b0
#define MSM_SDW_RX8_RX_PATH_SEC5 0x03b8
#define MSM_SDW_RX8_RX_PATH_SEC6 0x03bc
#define MSM_SDW_RX8_RX_PATH_SEC7 0x03c0
#define MSM_SDW_RX8_RX_PATH_MIX_SEC0 0x03c4
#define MSM_SDW_RX8_RX_PATH_MIX_SEC1 0x03c8
/* Page-C Registers */
#define MSM_SDW_BOOST0_BOOST_PATH_CTL 0x0064
#define MSM_SDW_BOOST0_BOOST_CTL 0x0068
#define MSM_SDW_BOOST0_BOOST_CFG1 0x006c
#define MSM_SDW_BOOST0_BOOST_CFG2 0x0070
#define MSM_SDW_BOOST1_BOOST_PATH_CTL 0x0084
#define MSM_SDW_BOOST1_BOOST_CTL 0x0088
#define MSM_SDW_BOOST1_BOOST_CFG1 0x008c
#define MSM_SDW_BOOST1_BOOST_CFG2 0x0090
#define MSM_SDW_AHB_BRIDGE_WR_DATA_0 0x00a4
#define MSM_SDW_AHB_BRIDGE_WR_DATA_1 0x00a8
#define MSM_SDW_AHB_BRIDGE_WR_DATA_2 0x00ac
#define MSM_SDW_AHB_BRIDGE_WR_DATA_3 0x00b0
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_0 0x00b4
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_1 0x00b8
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_2 0x00bc
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_3 0x00c0
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_0 0x00c4
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_1 0x00c8
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_2 0x00cc
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_3 0x00d0
#define MSM_SDW_AHB_BRIDGE_RD_DATA_0 0x00d4
#define MSM_SDW_AHB_BRIDGE_RD_DATA_1 0x00d8
#define MSM_SDW_AHB_BRIDGE_RD_DATA_2 0x00dc
#define MSM_SDW_AHB_BRIDGE_RD_DATA_3 0x00e0
#define MSM_SDW_AHB_BRIDGE_ACCESS_CFG 0x00e4
#define MSM_SDW_AHB_BRIDGE_ACCESS_STATUS 0x00e8
/* Page-D Registers */
#define MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL 0x0104
#define MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL 0x0108
#define MSM_SDW_CLK_RST_CTRL_SWR_CONTROL 0x010c
#define MSM_SDW_TOP_TOP_CFG0 0x0204
#define MSM_SDW_TOP_TOP_CFG1 0x0208
#define MSM_SDW_TOP_RX_I2S_CTL 0x020c
#define MSM_SDW_TOP_TX_I2S_CTL 0x0210
#define MSM_SDW_TOP_I2S_CLK 0x0214
#define MSM_SDW_TOP_RX7_PATH_INPUT0_MUX 0x0218
#define MSM_SDW_TOP_RX7_PATH_INPUT1_MUX 0x021c
#define MSM_SDW_TOP_RX8_PATH_INPUT0_MUX 0x0220
#define MSM_SDW_TOP_RX8_PATH_INPUT1_MUX 0x0224
#define MSM_SDW_TOP_FREQ_MCLK 0x0228
#define MSM_SDW_TOP_DEBUG_BUS_SEL 0x022c
#define MSM_SDW_TOP_DEBUG_EN 0x0230
#define MSM_SDW_TOP_I2S_RESET 0x0234
#define MSM_SDW_TOP_BLOCKS_RESET 0x0238
#endif

161
sound/soc/codecs/msm_sdw/msm_sdw_regmap.c Normal file
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/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/regmap.h>
#include "msm_sdw.h"
static const struct reg_default msm_sdw_defaults[] = {
/* Page #10 registers */
{ MSM_SDW_PAGE_REGISTER, 0x00 },
{ MSM_SDW_TX9_SPKR_PROT_PATH_CTL, 0x02 },
{ MSM_SDW_TX9_SPKR_PROT_PATH_CFG0, 0x00 },
{ MSM_SDW_TX10_SPKR_PROT_PATH_CTL, 0x02 },
{ MSM_SDW_TX10_SPKR_PROT_PATH_CFG0, 0x00 },
{ MSM_SDW_TX11_SPKR_PROT_PATH_CTL, 0x02 },
{ MSM_SDW_TX11_SPKR_PROT_PATH_CFG0, 0x00 },
{ MSM_SDW_TX12_SPKR_PROT_PATH_CTL, 0x02 },
{ MSM_SDW_TX12_SPKR_PROT_PATH_CFG0, 0x00 },
/* Page #11 registers */
{ MSM_SDW_COMPANDER7_CTL0, 0x60 },
{ MSM_SDW_COMPANDER7_CTL1, 0xdb },
{ MSM_SDW_COMPANDER7_CTL2, 0xff },
{ MSM_SDW_COMPANDER7_CTL3, 0x35 },
{ MSM_SDW_COMPANDER7_CTL4, 0xff },
{ MSM_SDW_COMPANDER7_CTL5, 0x00 },
{ MSM_SDW_COMPANDER7_CTL6, 0x01 },
{ MSM_SDW_COMPANDER8_CTL0, 0x60 },
{ MSM_SDW_COMPANDER8_CTL1, 0xdb },
{ MSM_SDW_COMPANDER8_CTL2, 0xff },
{ MSM_SDW_COMPANDER8_CTL3, 0x35 },
{ MSM_SDW_COMPANDER8_CTL4, 0xff },
{ MSM_SDW_COMPANDER8_CTL5, 0x00 },
{ MSM_SDW_COMPANDER8_CTL6, 0x01 },
{ MSM_SDW_RX7_RX_PATH_CTL, 0x04 },
{ MSM_SDW_RX7_RX_PATH_CFG0, 0x00 },
{ MSM_SDW_RX7_RX_PATH_CFG2, 0x8f },
{ MSM_SDW_RX7_RX_VOL_CTL, 0x00 },
{ MSM_SDW_RX7_RX_PATH_MIX_CTL, 0x04 },
{ MSM_SDW_RX7_RX_VOL_MIX_CTL, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC2, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC3, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC5, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC6, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC7, 0x00 },
{ MSM_SDW_RX7_RX_PATH_MIX_SEC1, 0x00 },
{ MSM_SDW_RX8_RX_PATH_CTL, 0x04 },
{ MSM_SDW_RX8_RX_PATH_CFG0, 0x00 },
{ MSM_SDW_RX8_RX_PATH_CFG2, 0x8f },
{ MSM_SDW_RX8_RX_VOL_CTL, 0x00 },
{ MSM_SDW_RX8_RX_PATH_MIX_CTL, 0x04 },
{ MSM_SDW_RX8_RX_VOL_MIX_CTL, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC2, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC3, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC5, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC6, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC7, 0x00 },
{ MSM_SDW_RX8_RX_PATH_MIX_SEC1, 0x00 },
/* Page #12 registers */
{ MSM_SDW_BOOST0_BOOST_PATH_CTL, 0x00 },
{ MSM_SDW_BOOST0_BOOST_CTL, 0xb2 },
{ MSM_SDW_BOOST0_BOOST_CFG1, 0x00 },
{ MSM_SDW_BOOST0_BOOST_CFG2, 0x00 },
{ MSM_SDW_BOOST1_BOOST_PATH_CTL, 0x00 },
{ MSM_SDW_BOOST1_BOOST_CTL, 0xb2 },
{ MSM_SDW_BOOST1_BOOST_CFG1, 0x00 },
{ MSM_SDW_BOOST1_BOOST_CFG2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_DATA_0, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_DATA_1, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_DATA_2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_DATA_3, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_0, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_1, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_3, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_0, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_1, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_3, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_DATA_0, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_DATA_1, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_DATA_2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_DATA_3, 0x00 },
{ MSM_SDW_AHB_BRIDGE_ACCESS_CFG, 0x0f },
{ MSM_SDW_AHB_BRIDGE_ACCESS_STATUS, 0x03 },
/* Page #13 registers */
{ MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
{ MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
{ MSM_SDW_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
{ MSM_SDW_TOP_TOP_CFG0, 0x00 },
{ MSM_SDW_TOP_TOP_CFG1, 0x00 },
{ MSM_SDW_TOP_RX_I2S_CTL, 0x0C },
{ MSM_SDW_TOP_TX_I2S_CTL, 0x00 },
{ MSM_SDW_TOP_I2S_CLK, 0x00 },
{ MSM_SDW_TOP_RX7_PATH_INPUT0_MUX, 0x00 },
{ MSM_SDW_TOP_RX7_PATH_INPUT1_MUX, 0x00 },
{ MSM_SDW_TOP_RX8_PATH_INPUT0_MUX, 0x00 },
{ MSM_SDW_TOP_RX8_PATH_INPUT1_MUX, 0x00 },
{ MSM_SDW_TOP_FREQ_MCLK, 0x00 },
{ MSM_SDW_TOP_DEBUG_BUS_SEL, 0x00 },
{ MSM_SDW_TOP_DEBUG_EN, 0x00 },
{ MSM_SDW_TOP_I2S_RESET, 0x00 },
{ MSM_SDW_TOP_BLOCKS_RESET, 0x00 },
};
static bool msm_sdw_is_readable_register(struct device *dev, unsigned int reg)
{
return msm_sdw_reg_readable[reg];
}
static bool msm_sdw_is_writeable_register(struct device *dev, unsigned int reg)
{
return msm_sdw_reg_writeable[reg];
}
static bool msm_sdw_is_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MSM_SDW_AHB_BRIDGE_WR_DATA_0:
case MSM_SDW_AHB_BRIDGE_WR_DATA_1:
case MSM_SDW_AHB_BRIDGE_WR_DATA_2:
case MSM_SDW_AHB_BRIDGE_WR_DATA_3:
case MSM_SDW_AHB_BRIDGE_WR_ADDR_0:
case MSM_SDW_AHB_BRIDGE_WR_ADDR_1:
case MSM_SDW_AHB_BRIDGE_WR_ADDR_2:
case MSM_SDW_AHB_BRIDGE_WR_ADDR_3:
case MSM_SDW_AHB_BRIDGE_RD_DATA_0:
case MSM_SDW_AHB_BRIDGE_RD_DATA_1:
case MSM_SDW_AHB_BRIDGE_RD_DATA_2:
case MSM_SDW_AHB_BRIDGE_RD_DATA_3:
case MSM_SDW_AHB_BRIDGE_RD_ADDR_0:
case MSM_SDW_AHB_BRIDGE_RD_ADDR_1:
case MSM_SDW_AHB_BRIDGE_RD_ADDR_2:
case MSM_SDW_AHB_BRIDGE_RD_ADDR_3:
case MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL:
case MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL:
return true;
default:
return false;
}
}
const struct regmap_config msm_sdw_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.reg_stride = 4,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = msm_sdw_defaults,
.num_reg_defaults = ARRAY_SIZE(msm_sdw_defaults),
.max_register = MSM_SDW_MAX_REGISTER,
.writeable_reg = msm_sdw_is_writeable_register,
.volatile_reg = msm_sdw_is_volatile_register,
.readable_reg = msm_sdw_is_readable_register,
};