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cnss2: Add time sync support for kiwi device

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Enable time sync feature for kiwi device which uses MHI registers
to get device time and uses shadow register #0 and #1 to get time
difference.

Change-Id: I72749c7b0328d278d9157adf254911280604ad60
This commit is contained in:
Yue Ma
2022-03-08 14:34:39 -08:00
committed by Gerrit - the friendly Code Review server
parent ce5d7eafbc
commit 35d040ea76
2 changed files with 57 additions and 11 deletions
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64
cnss2/pci.c
View File

@@ -2307,8 +2307,16 @@ static int cnss_pci_get_device_timestamp(struct cnss_pci_data *pci_priv,
return -EINVAL; return -EINVAL;
} }
cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL3, &low); switch (pci_priv->device_id) {
cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL4, &high); case KIWI_DEVICE_ID:
cnss_pci_reg_read(pci_priv, PCIE_MHI_TIME_LOW, &low);
cnss_pci_reg_read(pci_priv, PCIE_MHI_TIME_HIGH, &high);
break;
default:
cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL3, &low);
cnss_pci_reg_read(pci_priv, WLAON_GLOBAL_COUNTER_CTRL4, &high);
break;
}
device_ticks = (u64)high << 32 | low; device_ticks = (u64)high << 32 | low;
do_div(device_ticks, plat_priv->device_freq_hz / 100000); do_div(device_ticks, plat_priv->device_freq_hz / 100000);
@@ -2319,16 +2327,56 @@ static int cnss_pci_get_device_timestamp(struct cnss_pci_data *pci_priv,
static void cnss_pci_enable_time_sync_counter(struct cnss_pci_data *pci_priv) static void cnss_pci_enable_time_sync_counter(struct cnss_pci_data *pci_priv)
{ {
switch (pci_priv->device_id) {
case KIWI_DEVICE_ID:
return;
default:
break;
}
cnss_pci_reg_write(pci_priv, WLAON_GLOBAL_COUNTER_CTRL5, cnss_pci_reg_write(pci_priv, WLAON_GLOBAL_COUNTER_CTRL5,
TIME_SYNC_ENABLE); TIME_SYNC_ENABLE);
} }
static void cnss_pci_clear_time_sync_counter(struct cnss_pci_data *pci_priv) static void cnss_pci_clear_time_sync_counter(struct cnss_pci_data *pci_priv)
{ {
switch (pci_priv->device_id) {
case KIWI_DEVICE_ID:
return;
default:
break;
}
cnss_pci_reg_write(pci_priv, WLAON_GLOBAL_COUNTER_CTRL5, cnss_pci_reg_write(pci_priv, WLAON_GLOBAL_COUNTER_CTRL5,
TIME_SYNC_CLEAR); TIME_SYNC_CLEAR);
} }
static void cnss_pci_time_sync_reg_update(struct cnss_pci_data *pci_priv,
u32 low, u32 high)
{
u32 time_reg_low = PCIE_SHADOW_REG_VALUE_0;
u32 time_reg_high = PCIE_SHADOW_REG_VALUE_1;
switch (pci_priv->device_id) {
case KIWI_DEVICE_ID:
/* Forward compatibility */
break;
default:
time_reg_low = PCIE_SHADOW_REG_VALUE_34;
time_reg_high = PCIE_SHADOW_REG_VALUE_35;
break;
}
cnss_pci_reg_write(pci_priv, time_reg_low, low);
cnss_pci_reg_write(pci_priv, time_reg_high, high);
cnss_pci_reg_read(pci_priv, time_reg_low, &low);
cnss_pci_reg_read(pci_priv, time_reg_high, &high);
cnss_pr_dbg("Updated time sync regs [0x%x] = 0x%x, [0x%x] = 0x%x\n",
time_reg_low, low, time_reg_high, high);
}
static int cnss_pci_update_timestamp(struct cnss_pci_data *pci_priv) static int cnss_pci_update_timestamp(struct cnss_pci_data *pci_priv)
{ {
struct cnss_plat_data *plat_priv = pci_priv->plat_priv; struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
@@ -2370,15 +2418,7 @@ static int cnss_pci_update_timestamp(struct cnss_pci_data *pci_priv)
low = offset & 0xFFFFFFFF; low = offset & 0xFFFFFFFF;
high = offset >> 32; high = offset >> 32;
cnss_pci_reg_write(pci_priv, PCIE_SHADOW_REG_VALUE_34, low); cnss_pci_time_sync_reg_update(pci_priv, low, high);
cnss_pci_reg_write(pci_priv, PCIE_SHADOW_REG_VALUE_35, high);
cnss_pci_reg_read(pci_priv, PCIE_SHADOW_REG_VALUE_34, &low);
cnss_pci_reg_read(pci_priv, PCIE_SHADOW_REG_VALUE_35, &high);
cnss_pr_dbg("Updated time sync regs [0x%x] = 0x%x, [0x%x] = 0x%x\n",
PCIE_SHADOW_REG_VALUE_34, low,
PCIE_SHADOW_REG_VALUE_35, high);
force_wake_put: force_wake_put:
cnss_pci_force_wake_put(pci_priv); cnss_pci_force_wake_put(pci_priv);
@@ -2430,6 +2470,7 @@ static int cnss_pci_start_time_sync_update(struct cnss_pci_data *pci_priv)
switch (pci_priv->device_id) { switch (pci_priv->device_id) {
case QCA6390_DEVICE_ID: case QCA6390_DEVICE_ID:
case QCA6490_DEVICE_ID: case QCA6490_DEVICE_ID:
case KIWI_DEVICE_ID:
break; break;
default: default:
return -EOPNOTSUPP; return -EOPNOTSUPP;
@@ -2450,6 +2491,7 @@ static void cnss_pci_stop_time_sync_update(struct cnss_pci_data *pci_priv)
switch (pci_priv->device_id) { switch (pci_priv->device_id) {
case QCA6390_DEVICE_ID: case QCA6390_DEVICE_ID:
case QCA6490_DEVICE_ID: case QCA6490_DEVICE_ID:
case KIWI_DEVICE_ID:
break; break;
default: default:
return; return;

4
cnss2/reg.h
View File

@@ -53,12 +53,16 @@
#define SHADOW_REG_COUNT 36 #define SHADOW_REG_COUNT 36
#define PCIE_SHADOW_REG_VALUE_0 0x8FC #define PCIE_SHADOW_REG_VALUE_0 0x8FC
#define PCIE_SHADOW_REG_VALUE_1 0x900
#define PCIE_SHADOW_REG_VALUE_34 0x984 #define PCIE_SHADOW_REG_VALUE_34 0x984
#define PCIE_SHADOW_REG_VALUE_35 0x988 #define PCIE_SHADOW_REG_VALUE_35 0x988
#define SHADOW_REG_INTER_COUNT 43 #define SHADOW_REG_INTER_COUNT 43
#define PCIE_SHADOW_REG_INTER_0 0x1E05000 #define PCIE_SHADOW_REG_INTER_0 0x1E05000
#define PCIE_MHI_TIME_LOW 0xA28
#define PCIE_MHI_TIME_HIGH 0xA2C
#define QDSS_APB_DEC_CSR_BASE 0x1C01000 #define QDSS_APB_DEC_CSR_BASE 0x1C01000
#define QDSS_APB_DEC_CSR_ETRIRQCTRL_OFFSET 0x6C #define QDSS_APB_DEC_CSR_ETRIRQCTRL_OFFSET 0x6C