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disp: msm: sde: update output_fence hw programming for pineapple

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Starting pineapple, the output_fence trigger_sel register is updated to be
more controllable. Instead of hardware choosing the output fence timing
based on detecting if panel is in video/cmd mode, this is explicitly set
by software. Add support in display driver for to correctly write to
trigger_sel register for video mode.

Change-Id: I76d8cfb644cebfd2f34f3017fc779b87fc52db1a
Signed-off-by: Grace An <quic_gracan@quicinc.com>
This commit is contained in:
Grace An
2023-02-27 14:09:04 -08:00
parent f8a9025152
commit 3564a2c6f2
4 changed files with 17 additions and 9 deletions
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17
msm/sde/sde_fence.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/ */
@@ -373,7 +373,8 @@ int sde_fence_register_hw_fences_wait(struct sde_hw_ctl *hw_ctl, struct dma_fenc
return ret; return ret;
} }
static int _arm_output_hw_fence(struct sde_hw_ctl *hw_ctl, u32 line_count, u32 debugfs_hw_fence) static int _arm_output_hw_fence(struct sde_hw_ctl *hw_ctl, bool vid_mode, u32 line_count,
u32 debugfs_hw_fence)
{ {
struct sde_hw_fence_data *data; struct sde_hw_fence_data *data;
u32 ipcc_out_signal; u32 ipcc_out_signal;
@@ -413,14 +414,16 @@ static int _arm_output_hw_fence(struct sde_hw_ctl *hw_ctl, u32 line_count, u32 d
if (line_count) if (line_count)
hw_ctl->ops.hw_fence_trigger_output_fence(hw_ctl, hw_ctl->ops.hw_fence_trigger_output_fence(hw_ctl,
HW_FENCE_TRIGGER_SEL_PROG_LINE_COUNT); HW_FENCE_TRIGGER_SEL_PROG_LINE_COUNT);
else if (vid_mode && (hw_ctl->caps->features & BIT(SDE_CTL_HW_FENCE_TRIGGER_SEL)))
hw_ctl->ops.hw_fence_trigger_output_fence(hw_ctl, HW_FENCE_TRIGGER_SEL_VID_MODE);
else else
hw_ctl->ops.hw_fence_trigger_output_fence(hw_ctl, HW_FENCE_TRIGGER_SEL_CTRL_DONE); hw_ctl->ops.hw_fence_trigger_output_fence(hw_ctl, HW_FENCE_TRIGGER_SEL_CMD_MODE);
return 0; return 0;
} }
static int _sde_fence_arm_output_hw_fence(struct sde_fence_context *ctx, u32 line_count, static int _sde_fence_arm_output_hw_fence(struct sde_fence_context *ctx, bool vid_mode,
u32 debugfs_hw_fence) u32 line_count, u32 debugfs_hw_fence)
{ {
struct sde_hw_ctl *hw_ctl = NULL; struct sde_hw_ctl *hw_ctl = NULL;
struct sde_fence *fc, *next; struct sde_fence *fc, *next;
@@ -457,7 +460,7 @@ static int _sde_fence_arm_output_hw_fence(struct sde_fence_context *ctx, u32 lin
/* arm dpu to trigger output hw-fence ipcc signal upon completion */ /* arm dpu to trigger output hw-fence ipcc signal upon completion */
if (hw_ctl) if (hw_ctl)
_arm_output_hw_fence(hw_ctl, line_count, debugfs_hw_fence); _arm_output_hw_fence(hw_ctl, vid_mode, line_count, debugfs_hw_fence);
return 0; return 0;
} }
@@ -539,7 +542,7 @@ exit:
/* arm dpu to trigger output hw-fence ipcc signal upon completion in vid-mode */ /* arm dpu to trigger output hw-fence ipcc signal upon completion in vid-mode */
if ((txq_updated && hw_ctl) || line_count) if ((txq_updated && hw_ctl) || line_count)
_sde_fence_arm_output_hw_fence(ctx, line_count, debugfs_hw_fence); _sde_fence_arm_output_hw_fence(ctx, vid_mode, line_count, debugfs_hw_fence);
return ret; return ret;
} }

5
msm/sde/sde_fence.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*/ */
@@ -16,8 +16,9 @@
#define CHAR_BIT 8 /* define this if limits.h not available */ #define CHAR_BIT 8 /* define this if limits.h not available */
#endif #endif
#define HW_FENCE_TRIGGER_SEL_CTRL_DONE 0x0 #define HW_FENCE_TRIGGER_SEL_CMD_MODE 0x0
#define HW_FENCE_TRIGGER_SEL_PROG_LINE_COUNT 0x1 #define HW_FENCE_TRIGGER_SEL_PROG_LINE_COUNT 0x1
#define HW_FENCE_TRIGGER_SEL_VID_MODE 0x2
#define SDE_INPUT_HW_FENCE_TIMESTAMP BIT(0) #define SDE_INPUT_HW_FENCE_TIMESTAMP BIT(0)
#define SDE_OUTPUT_HW_FENCE_TIMESTAMP BIT(1) #define SDE_OUTPUT_HW_FENCE_TIMESTAMP BIT(1)

2
msm/sde/sde_hw_catalog.c
View File

@@ -5484,6 +5484,8 @@ static void _sde_hw_fence_caps(struct sde_mdss_cfg *sde_cfg)
for (i = 0; i < sde_cfg->ctl_count; i++) { for (i = 0; i < sde_cfg->ctl_count; i++) {
ctl = sde_cfg->ctl + i; ctl = sde_cfg->ctl + i;
set_bit(SDE_CTL_HW_FENCE, &ctl->features); set_bit(SDE_CTL_HW_FENCE, &ctl->features);
if (SDE_HW_MAJOR(sde_cfg->hw_rev) >= SDE_HW_MAJOR(SDE_HW_VER_A00))
set_bit(SDE_CTL_HW_FENCE_TRIGGER_SEL, &ctl->features);
} }
} }

2
msm/sde/sde_hw_catalog.h
View File

@@ -594,6 +594,7 @@ enum {
* @SDE_CTL_UIDLE CTL supports uidle * @SDE_CTL_UIDLE CTL supports uidle
* @SDE_CTL_UNIFIED_DSPP_FLUSH CTL supports only one flush bit for DSPP * @SDE_CTL_UNIFIED_DSPP_FLUSH CTL supports only one flush bit for DSPP
* @SDE_CTL_HW_FENCE CTL supports hw fencing * @SDE_CTL_HW_FENCE CTL supports hw fencing
* @SDE_CTL_HW_FENCE_TRIGGER_SEL CTL supports SW selection of cmd/vid modes for trigger sel
* @SDE_CTL_MAX * @SDE_CTL_MAX
*/ */
enum { enum {
@@ -604,6 +605,7 @@ enum {
SDE_CTL_UIDLE, SDE_CTL_UIDLE,
SDE_CTL_UNIFIED_DSPP_FLUSH, SDE_CTL_UNIFIED_DSPP_FLUSH,
SDE_CTL_HW_FENCE, SDE_CTL_HW_FENCE,
SDE_CTL_HW_FENCE_TRIGGER_SEL,
SDE_CTL_MAX SDE_CTL_MAX
}; };