Merge "disp: msm: dsi: Use macros in DSI_R32/DSI_W32 for registers offset"

msm/dsi/dsi_ctrl_hw_cmn.c

@@ -1746,26 +1746,26 @@ int dsi_ctrl_hw_cmn_ctrl_reset(struct dsi_ctrl_hw *ctrl,
 
 	DSI_CTRL_HW_DBG(ctrl, "DSI CTRL and PHY reset, mask=%d\n", mask);
 
-	data = DSI_R32(ctrl, 0x0004);
+	data = DSI_R32(ctrl, DSI_CTRL);
 	/* Disable DSI video mode */
-	DSI_W32(ctrl, 0x004, (data & ~BIT(1)));
+	DSI_W32(ctrl, DSI_CTRL, (data & ~BIT(1)));
 	wmb(); /* ensure register committed */
 	/* Disable DSI controller */
-	DSI_W32(ctrl, 0x004, (data & ~(BIT(0) | BIT(1))));
+	DSI_W32(ctrl, DSI_CTRL, (data & ~(BIT(0) | BIT(1))));
 	wmb(); /* ensure register committed */
 	/* "Force On" all dynamic clocks */
-	DSI_W32(ctrl, 0x11c, 0x100a00);
+	DSI_W32(ctrl, DSI_CLK_CTRL, 0x100a00);
 
 	/* DSI_SW_RESET */
-	DSI_W32(ctrl, 0x118, 0x1);
+	DSI_W32(ctrl, DSI_SOFT_RESET, 0x1);
 	wmb(); /* ensure register is committed */
-	DSI_W32(ctrl, 0x118, 0x0);
+	DSI_W32(ctrl, DSI_SOFT_RESET, 0x0);
 	wmb(); /* ensure register is committed */
 
 	/* Remove "Force On" all dynamic clocks */
-	DSI_W32(ctrl, 0x11c, 0x00);
+	DSI_W32(ctrl, DSI_CLK_CTRL, 0x00);
 	/* Enable DSI controller */
-	DSI_W32(ctrl, 0x004, (data & ~BIT(1)));
+	DSI_W32(ctrl, DSI_CTRL, (data & ~BIT(1)));
 	wmb(); /* ensure register committed */
 
 	return rc;
@@ -1780,7 +1780,7 @@ void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en)
 	u32 lp_rx_clear = BIT(4);
 	u32 pll_unlock_clear = BIT(16);
 
-	reg = DSI_R32(ctrl, 0x10c);
+	reg = DSI_R32(ctrl, DSI_ERR_INT_MASK0);
 
 	/*
 	 * Before unmasking we should clear the corresponding error status bits
@@ -1795,8 +1795,8 @@ void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en)
 		} else {
 			reg &= ~(0x1f << 16);
 			reg &= ~BIT(9);
-			fifo_status = DSI_R32(ctrl, 0x00c);
-			DSI_W32(ctrl, 0x00c, fifo_status | overflow_clear);
+			fifo_status = DSI_R32(ctrl, DSI_FIFO_STATUS);
+			DSI_W32(ctrl, DSI_FIFO_STATUS, fifo_status | overflow_clear);
 		}
 	}
 
@@ -1805,8 +1805,8 @@ void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en)
 			reg |= (0x1b << 26);
 		else {
 			reg &= ~(0x1b << 26);
-			fifo_status = DSI_R32(ctrl, 0x00c);
-			DSI_W32(ctrl, 0x00c, fifo_status | underflow_clear);
+			fifo_status = DSI_R32(ctrl, DSI_FIFO_STATUS);
+			DSI_W32(ctrl, DSI_FIFO_STATUS, fifo_status | underflow_clear);
 		}
 	}
 
@@ -1815,8 +1815,8 @@ void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en)
 			reg |= (0x7 << 23);
 		else {
 			reg &= ~(0x7 << 23);
-			timeout_status = DSI_R32(ctrl, 0x0c0);
-			DSI_W32(ctrl, 0x0c0, timeout_status | lp_rx_clear);
+			timeout_status = DSI_R32(ctrl, DSI_TIMEOUT_STATUS);
+			DSI_W32(ctrl, DSI_TIMEOUT_STATUS, timeout_status | lp_rx_clear);
 		}
 	}
 
@@ -1830,7 +1830,7 @@ void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en)
 		}
 	}
 
-	DSI_W32(ctrl, 0x10c, reg);
+	DSI_W32(ctrl, DSI_ERR_INT_MASK0, reg);
 	wmb(); /* ensure error is masked */
 }
 
@@ -1839,7 +1839,7 @@ void dsi_ctrl_hw_cmn_error_intr_ctrl(struct dsi_ctrl_hw *ctrl, bool en)
 	u32 reg = 0;
 	u32 dsi_total_mask = 0x2222AA02;
 
-	reg = DSI_R32(ctrl, 0x110);
+	reg = DSI_R32(ctrl, DSI_INT_CTRL);
 	reg &= dsi_total_mask;
 
 	if (en)
@@ -1847,7 +1847,7 @@ void dsi_ctrl_hw_cmn_error_intr_ctrl(struct dsi_ctrl_hw *ctrl, bool en)
 	else
 		reg &= ~BIT(25);
 
-	DSI_W32(ctrl, 0x110, reg);
+	DSI_W32(ctrl, DSI_INT_CTRL, reg);
 	wmb(); /* ensure error is masked */
 }
 
@@ -1855,7 +1855,7 @@ u32 dsi_ctrl_hw_cmn_get_error_mask(struct dsi_ctrl_hw *ctrl)
 {
 	u32 reg = 0;
 
-	reg = DSI_R32(ctrl, 0x10c);
+	reg = DSI_R32(ctrl, DSI_ERR_INT_MASK0);
 
 	return reg;
 }
@@ -1864,7 +1864,7 @@ u32 dsi_ctrl_hw_cmn_get_hw_version(struct dsi_ctrl_hw *ctrl)
 {
 	u32 reg = 0;
 
-	reg = DSI_R32(ctrl, 0x0);
+	reg = DSI_R32(ctrl, DSI_HW_VERSION);
 
 	return reg;
 }