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@@ -0,0 +1,345 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/*
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+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
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+ */
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+
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+#include <linux/iopoll.h>
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+#include <linux/slab.h>
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+#include <media/cam_tfe.h>
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+#include <media/cam_defs.h>
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+
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+#include "cam_top_tpg_core.h"
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+#include "cam_soc_util.h"
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+#include "cam_io_util.h"
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+#include "cam_debug_util.h"
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+#include "cam_top_tpg_ver3.h"
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+
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+static int cam_top_tpg_ver3_get_hw_caps(
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+ void *hw_priv,
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+ void *get_hw_cap_args,
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+ uint32_t arg_size)
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+{
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+ int rc = 0;
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+ struct cam_top_tpg_hw_caps *hw_caps;
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+ struct cam_top_tpg_hw *tpg_hw;
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+ const struct cam_top_tpg_ver3_reg_offset *tpg_reg;
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+ struct cam_hw_info *tpg_hw_info;
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+
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+ if (!hw_priv || !get_hw_cap_args) {
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+ CAM_ERR(CAM_ISP, "TPG: Invalid args");
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+ return -EINVAL;
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+ }
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+
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+ tpg_hw_info = (struct cam_hw_info *)hw_priv;
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+ tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info;
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+ hw_caps = (struct cam_top_tpg_hw_caps *) get_hw_cap_args;
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+ tpg_reg = tpg_hw->tpg_info->tpg_reg;
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+
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+ hw_caps->major_version = tpg_reg->major_version;
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+ hw_caps->minor_version = tpg_reg->minor_version;
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+ hw_caps->version_incr = tpg_reg->version_incr;
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+
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+ CAM_DBG(CAM_ISP,
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+ "TPG:%d major:%d minor:%d ver :%d",
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+ tpg_hw->hw_intf->hw_idx, hw_caps->major_version,
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+ hw_caps->minor_version, hw_caps->version_incr);
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+
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+ return rc;
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+}
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+
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+static int cam_top_tpg_ver3_reserve(
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+ void *hw_priv,
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+ void *reserve_args,
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+ uint32_t arg_size)
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+{
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+ int rc = 0;
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+ struct cam_top_tpg_hw *tpg_hw;
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+ struct cam_hw_info *tpg_hw_info;
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+ struct cam_top_tpg_ver3_reserve_args *reserv;
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+ struct cam_top_tpg_cfg *tpg_data;
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+ uint32_t encode_format = 0;
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+ uint32_t i;
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+
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+ if (!hw_priv || !reserve_args || (arg_size !=
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+ sizeof(struct cam_top_tpg_ver3_reserve_args))) {
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+ CAM_ERR(CAM_ISP, "TPG: Invalid args");
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+ return -EINVAL;
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+ }
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+
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+ tpg_hw_info = (struct cam_hw_info *)hw_priv;
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+ tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info;
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+ reserv = (struct cam_top_tpg_ver3_reserve_args *)reserve_args;
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+
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+ if (reserv->num_inport <= 0 ||
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+ reserv->num_inport > CAM_TOP_TPG_MAX_SUPPORTED_DT) {
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+ CAM_ERR_RATE_LIMIT(CAM_ISP, "TPG: %u invalid input num port:%d",
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+ tpg_hw->hw_intf->hw_idx, reserv->num_inport);
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+ return -EINVAL;
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+ }
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+
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+ mutex_lock(&tpg_hw->hw_info->hw_mutex);
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+ if (tpg_hw->tpg_res.res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) {
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+ rc = -EINVAL;
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+ goto error;
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+ }
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+
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+ if ((reserv->in_port->lane_num <= 0 ||
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+ reserv->in_port->lane_num > 4) ||
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+ (reserv->in_port->lane_type >= 2)) {
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+ CAM_ERR_RATE_LIMIT(CAM_ISP, "TPG:%u invalid input %d %d",
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+ tpg_hw->hw_intf->hw_idx,
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+ reserv->in_port->lane_num,
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+ reserv->in_port->lane_type);
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+ rc = -EINVAL;
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+ goto error;
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+ }
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+
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+ tpg_data = (struct cam_top_tpg_cfg *)tpg_hw->tpg_res.res_priv;
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+
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+ for (i = 0; i < reserv->in_port->num_valid_vc_dt; i++) {
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+ if (reserv->in_port->dt[i] > 0x3f ||
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+ reserv->in_port->vc[i] > 0x1f) {
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+ CAM_ERR(CAM_ISP, "TPG:%u Invalid vc:%d dt %d",
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+ tpg_hw->hw_intf->hw_idx,
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+ reserv->in_port->vc[i],
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+ reserv->in_port->dt[i]);
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+ rc = -EINVAL;
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+ goto error;
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+ }
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+ tpg_data->vc_num[i] = reserv->in_port->vc[i];
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+ tpg_data->dt_cfg[i].data_type = reserv->in_port->dt[i];
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+ }
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+
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+ rc = cam_top_tpg_get_format(reserv->in_port->format,
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+ &encode_format);
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+ if (rc)
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+ goto error;
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+
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+
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+ CAM_DBG(CAM_ISP, "TPG: %u enter", tpg_hw->hw_intf->hw_idx);
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+
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+ tpg_data = (struct cam_top_tpg_cfg *)tpg_hw->tpg_res.res_priv;
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+ tpg_data->phy_sel = reserv->in_port->lane_type;
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+ tpg_data->num_active_lanes = reserv->in_port->lane_num;
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+ tpg_data->h_blank_count = reserv->in_port->hbi_cnt;
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+ tpg_data->v_blank_count = 600;
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+ tpg_data->num_active_dts = reserv->in_port->num_valid_vc_dt;
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+
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+ for (i = 0; i < reserv->in_port->num_valid_vc_dt; i++) {
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+ tpg_data->dt_cfg[i].encode_format = encode_format;
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+ tpg_data->dt_cfg[i].frame_height = reserv->in_port->height;
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+
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+ if (reserv->in_port->usage_type)
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+ tpg_data->dt_cfg[i].frame_width =
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+ ((reserv->in_port->right_stop -
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+ reserv->in_port->left_start) + 1);
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+ else
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+ tpg_data->dt_cfg[i].frame_width =
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+ reserv->in_port->left_width;
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+ }
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+
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+ CAM_DBG(CAM_ISP,
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+ "TPG:%u vc_num:%d dt:%d phy:%d lines:%d pattern:%d format:%d",
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+ tpg_hw->hw_intf->hw_idx,
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+ tpg_data->vc_num, tpg_data->dt_cfg[0].data_type,
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+ tpg_data->phy_sel, tpg_data->num_active_lanes,
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+ tpg_data->pix_pattern,
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+ tpg_data->dt_cfg[0].encode_format);
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+
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+ CAM_DBG(CAM_ISP, "TPG:%u height:%d width:%d h blank:%d v blank:%d",
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+ tpg_hw->hw_intf->hw_idx,
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+ tpg_data->dt_cfg[0].frame_height,
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+ tpg_data->dt_cfg[0].frame_width,
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+ tpg_data->h_blank_count,
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+ tpg_data->v_blank_count);
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+
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+ reserv->node_res = &tpg_hw->tpg_res;
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+ tpg_hw->tpg_res.res_state = CAM_ISP_RESOURCE_STATE_RESERVED;
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+error:
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+ mutex_unlock(&tpg_hw->hw_info->hw_mutex);
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+ CAM_DBG(CAM_ISP, "exit rc %u", rc);
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+
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+ return rc;
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+}
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+
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+static int cam_top_tpg_ver3_start(
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+ void *hw_priv,
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+ void *start_args,
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+ uint32_t arg_size)
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+{
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+ int rc = 0;
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+ struct cam_top_tpg_hw *tpg_hw;
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+ struct cam_hw_info *tpg_hw_info;
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+ struct cam_hw_soc_info *soc_info;
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+ struct cam_isp_resource_node *tpg_res;
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+ struct cam_top_tpg_ver3_reg_offset *tpg_reg;
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+ struct cam_top_tpg_cfg *tpg_data;
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+ uint32_t i, val;
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+
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+ if (!hw_priv || !start_args ||
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+ (arg_size != sizeof(struct cam_isp_resource_node))) {
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+ CAM_ERR(CAM_ISP, "TPG: Invalid args");
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+ return -EINVAL;
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+ }
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+
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+ tpg_hw_info = (struct cam_hw_info *)hw_priv;
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+ tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info;
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+ tpg_reg = tpg_hw->tpg_info->tpg_reg;
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+ tpg_res = (struct cam_isp_resource_node *)start_args;
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+ tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_priv;
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+ soc_info = &tpg_hw->hw_info->soc_info;
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+
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+ if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) ||
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+ (tpg_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED)) {
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+ CAM_ERR(CAM_ISP, "TPG:%d Invalid Res type:%d res_state:%d",
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+ tpg_hw->hw_intf->hw_idx,
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+ tpg_res->res_type, tpg_res->res_state);
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+ rc = -EINVAL;
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+ goto end;
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+ }
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+
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+ cam_io_w_mb(1, soc_info->reg_map[0].mem_base + tpg_reg->tpg_top_clear);
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+
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+ for (i = 0; i < tpg_data->num_active_dts; i++) {
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+ val = (((tpg_data->dt_cfg[i].frame_width & 0xFFFF) << 16) |
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+ (tpg_data->dt_cfg[i].frame_height & 0xFFFF));
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+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_dt_0_cfg_0 + 0x60 * i);
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+
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+ cam_io_w_mb(tpg_data->dt_cfg[i].data_type,
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+ soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_dt_0_cfg_1 + 0x60 * i);
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+ val = ((tpg_data->dt_cfg[i].encode_format & 0xF) <<
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+ tpg_reg->tpg_dt_encode_format_shift) |
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+ tpg_reg->tpg_payload_mode_color;
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+
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+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_dt_0_cfg_2 + 0x60 * i);
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+
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+ val = (1 << tpg_reg->tpg_split_en_shift);
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+ val |= tpg_data->pix_pattern;
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+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_color_bar_cfg + 0x60 * i);
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+
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+ /*
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+ * if hblank is notset configureHBlank count 500 and
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+ * V blank count is 600
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+ */
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+
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+ if (tpg_data->h_blank_count)
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+ cam_io_w_mb(tpg_data->h_blank_count,
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+ soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_hbi_cfg + 0x60 * i);
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+ else
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+ cam_io_w_mb(0x1F4,
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+ soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_hbi_cfg + 0x60 * i);
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+
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+ if (tpg_data->v_blank_count)
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+ cam_io_w_mb(tpg_data->h_blank_count,
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+ soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_vbi_cfg + 0x60 * i);
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+ else
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+ cam_io_w_mb(0x258,
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+ soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_vbi_cfg + 0x60 * i);
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+
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+ cam_io_w_mb(0x12345678, soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_lfsr_seed + 0x60 * i);
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+
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+ val = (((tpg_data->num_active_dts-1) <<
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+ tpg_reg->tpg_num_dts_shift_val) | tpg_data->vc_num[i]);
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+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_vc0_cfg0 + 0x60 * i);
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+ }
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+
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+ cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_top_irq_mask);
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+
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+ val = ((tpg_data->num_active_dts - 1) <<
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+ (tpg_reg->tpg_num_active_vcs_shift) |
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+ (tpg_data->num_active_lanes - 1) <<
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+ tpg_reg->tpg_num_active_lanes_shift) |
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+ (tpg_data->vc_dt_pattern_id) <<
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+ (tpg_reg->tpg_vc_dt_pattern_id_shift) |
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+ (tpg_data->phy_sel << tpg_reg->tpg_cphy_dphy_sel_shift_val) |
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+ (1 << tpg_reg->tpg_en_shift_val);
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+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_ctrl);
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+
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+
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+ tpg_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
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+
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+ val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_hw_version);
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+ CAM_DBG(CAM_ISP, "TPG:%d TPG HW version: 0x%x started",
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+ tpg_hw->hw_intf->hw_idx, val);
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+
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+end:
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+ return rc;
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+}
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+
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+static int cam_top_tpg_ver3_stop(
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+ void *hw_priv,
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+ void *stop_args,
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+ uint32_t arg_size)
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+{
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+ int rc = 0;
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+ struct cam_top_tpg_hw *tpg_hw;
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+ struct cam_hw_info *tpg_hw_info;
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+ struct cam_hw_soc_info *soc_info;
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+ struct cam_isp_resource_node *tpg_res;
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+ const struct cam_top_tpg_ver3_reg_offset *tpg_reg;
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+ struct cam_top_tpg_cfg *tpg_data;
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+
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+ if (!hw_priv || !stop_args ||
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+ (arg_size != sizeof(struct cam_isp_resource_node))) {
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+ CAM_ERR(CAM_ISP, "TPG: Invalid args");
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+ return -EINVAL;
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+ }
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+
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+ tpg_hw_info = (struct cam_hw_info *)hw_priv;
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+ tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info;
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+ tpg_reg = tpg_hw->tpg_info->tpg_reg;
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+ tpg_res = (struct cam_isp_resource_node *) stop_args;
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+ tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_state;
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+ soc_info = &tpg_hw->hw_info->soc_info;
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+
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+ if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) ||
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+ (tpg_res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING)) {
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+ CAM_DBG(CAM_ISP, "TPG:%d Invalid Res type:%d res_state:%d",
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+ tpg_hw->hw_intf->hw_idx,
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+ tpg_res->res_type, tpg_res->res_state);
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+ rc = -EINVAL;
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+ goto end;
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+ }
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+
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+ cam_io_w_mb(0, soc_info->reg_map[0].mem_base + tpg_reg->tpg_ctrl);
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+
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+ cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_top_irq_mask);
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+
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+ cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_top_irq_clear);
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+
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+ cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
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+ tpg_reg->tpg_top_irq_cmd);
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+
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+ cam_io_w_mb(1, soc_info->reg_map[0].mem_base + tpg_reg->tpg_top_clear);
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+
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+ tpg_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED;
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+
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+ CAM_DBG(CAM_ISP, "TPG:%d stopped", tpg_hw->hw_intf->hw_idx);
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+end:
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+ return rc;
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+}
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+
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+int cam_top_tpg_ver3_init(
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+ struct cam_top_tpg_hw *tpg_hw)
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+{
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+ tpg_hw->hw_intf->hw_ops.get_hw_caps = cam_top_tpg_ver3_get_hw_caps;
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|
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+ tpg_hw->hw_intf->hw_ops.reserve = cam_top_tpg_ver3_reserve;
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|
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+ tpg_hw->hw_intf->hw_ops.start = cam_top_tpg_ver3_start;
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+ tpg_hw->hw_intf->hw_ops.stop = cam_top_tpg_ver3_stop;
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|
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+
|
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+ return 0;
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|
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+}
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Vishalsingh Hajeri