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@@ -66,6 +66,9 @@
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#define SDE_HW_BLK_NAME_LEN 16
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#define SDE_HW_BLK_NAME_LEN 16
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+/* default size of valid register space for MDSS_HW block (offset 0) */
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+#define DEFAULT_MDSS_HW_BLOCK_SIZE 0x5C
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+
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#define MAX_IMG_WIDTH 0x3fff
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#define MAX_IMG_WIDTH 0x3fff
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#define MAX_IMG_HEIGHT 0x3fff
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#define MAX_IMG_HEIGHT 0x3fff
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@@ -1423,6 +1426,7 @@ struct sde_limit_cfg {
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* @has_sui_blendstage flag to indicate secure-ui has a blendstage restriction
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* @has_sui_blendstage flag to indicate secure-ui has a blendstage restriction
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* @has_cursor indicates if hardware cursor is supported
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* @has_cursor indicates if hardware cursor is supported
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* @has_vig_p010 indicates if vig pipe supports p010 format
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* @has_vig_p010 indicates if vig pipe supports p010 format
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+ * @mdss_hw_block_size Max offset of MDSS_HW block (0 offset), used for debug
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* @inline_rot_formats formats supported by the inline rotator feature
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* @inline_rot_formats formats supported by the inline rotator feature
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* @irq_offset_list list of sde_intr_irq_offsets to initialize irq table
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* @irq_offset_list list of sde_intr_irq_offsets to initialize irq table
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* @rc_count number of rounded corner hardware instances
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* @rc_count number of rounded corner hardware instances
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@@ -1485,6 +1489,7 @@ struct sde_mdss_cfg {
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bool has_hdr_plus;
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bool has_hdr_plus;
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bool has_cursor;
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bool has_cursor;
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bool has_vig_p010;
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bool has_vig_p010;
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+ u32 mdss_hw_block_size;
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u32 mdss_count;
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u32 mdss_count;
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struct sde_mdss_base_cfg mdss[MAX_BLOCKS];
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struct sde_mdss_base_cfg mdss[MAX_BLOCKS];
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