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qcacmn: Flush the PCIe window select config before device access

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PCIe window select config reg update goes on different NoC and
actual PCIe device register access goes on the different NoC.
If there is delay in window select reg config, it can result in
access some other PCIe IO memory access and will result in actual
register write lost issue. Make sure to flush the window select
reg write before actual device reg access.

Change-Id: I1fe17aad7ae8fd5dea7a618273d9cd813b236a85
CRs-Fixed: 2687676
This commit is contained in:
Manjunathappa Prakash
2020-05-27 16:29:59 -07:00
committed by nshrivas
parent d30eab103c
commit 32acca2463
1 changed files with 4 additions and 24 deletions
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28
hal/wifi3.0/hal_api.h
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@@ -158,15 +158,6 @@ static inline void hal_unlock_reg_access(struct hal_soc *soc,
#endif
#ifdef PCIE_REG_WINDOW_LOCAL_NO_CACHE
static inline void hal_select_window(struct hal_soc *hal_soc, uint32_t offset)
{
uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
WINDOW_ENABLE_BIT | window);
hal_soc->register_window = window;
}
/**
* hal_select_window_confirm() - write remap window register and
check writing result
@@ -185,17 +176,6 @@ static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
WINDOW_ENABLE_BIT | window);
}
#else
static inline void hal_select_window(struct hal_soc *hal_soc, uint32_t offset)
{
uint32_t window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
if (window != hal_soc->register_window) {
qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
WINDOW_ENABLE_BIT | window);
hal_soc->register_window = window;
}
}
static inline void hal_select_window_confirm(struct hal_soc *hal_soc,
uint32_t offset)
{
@@ -272,7 +252,7 @@ static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
qdf_iowrite32(new_addr, value);
} else {
hal_lock_reg_access(hal_soc, &flags);
hal_select_window(hal_soc, offset);
hal_select_window_confirm(hal_soc, offset);
qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
(offset & WINDOW_RANGE_MASK), value);
hal_unlock_reg_access(hal_soc, &flags);
@@ -315,7 +295,7 @@ static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
qdf_iowrite32(new_addr, value);
} else {
hal_lock_reg_access(hal_soc, &flags);
hal_select_window(hal_soc, offset);
hal_select_window_confirm(hal_soc, offset);
qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_START +
(offset & WINDOW_RANGE_MASK), value);
hal_unlock_reg_access(hal_soc, &flags);
@@ -482,7 +462,7 @@ static inline uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
}
hal_lock_reg_access(hal_soc, &flags);
hal_select_window(hal_soc, offset);
hal_select_window_confirm(hal_soc, offset);
ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
(offset & WINDOW_RANGE_MASK));
hal_unlock_reg_access(hal_soc, &flags);
@@ -518,7 +498,7 @@ uint32_t hal_read32_mb(struct hal_soc *hal_soc, uint32_t offset)
ret = qdf_ioread32(new_addr);
} else {
hal_lock_reg_access(hal_soc, &flags);
hal_select_window(hal_soc, offset);
hal_select_window_confirm(hal_soc, offset);
ret = qdf_ioread32(hal_soc->dev_base_addr + WINDOW_START +
(offset & WINDOW_RANGE_MASK));
hal_unlock_reg_access(hal_soc, &flags);