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@@ -80,6 +80,8 @@
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#define BW_160_MHZ 160
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#define BW_40_MHZ 40
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+#define MAX_NUM_PWR_LEVEL 16
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+
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/**
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* enum dfs_reg - DFS region
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* @DFS_UNINIT_REGION: un-initialized region
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@@ -1313,4 +1315,38 @@ enum reg_phymode {
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REG_PHYMODE_MAX,
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};
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+/**
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+ * struct chan_power_info - TPE containing power info per channel chunk
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+ * @chan_cfreq: channel center freq (MHz)
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+ * @tx_power: transmit power (dBm)
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+ */
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+struct chan_power_info {
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+ qdf_freq_t chan_cfreq;
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+ uint8_t tx_power;
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+};
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+
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+/**
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+ * struct reg_tpc_power_info - regulatory TPC power info
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+ * @is_psd_power: is PSD power or not
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+ * @eirp_power: Maximum EIRP power (dBm), valid only if power is PSD
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+ * @power_type_6g: type of power (SP/LPI/VLP)
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+ * @num_pwr_levels: number of power levels
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+ * @reg_max: Array of maximum TX power (dBm) per PSD value
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+ * @ap_constraint_power: AP constraint power (dBm)
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+ * @frequency: Array of operating frequency
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+ * @tpe: TPE values processed from TPE IE
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+ * @chan_power_info: power info to send to FW
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+ */
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+struct reg_tpc_power_info {
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+ bool is_psd_power;
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+ uint8_t eirp_power;
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+ uint8_t power_type_6g;
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+ uint8_t num_pwr_levels;
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+ uint8_t reg_max[MAX_NUM_PWR_LEVEL];
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+ uint8_t ap_constraint_power;
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+ qdf_freq_t frequency[MAX_NUM_PWR_LEVEL];
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+ uint8_t tpe[MAX_NUM_PWR_LEVEL];
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+ struct chan_power_info chan_power_info[MAX_NUM_PWR_LEVEL];
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+};
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+
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#endif
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