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qcacmn: Support QCA6290 target type

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Add device id for QCA6290 emulation platform.
Add target def support for QCA6290
Needs HIF_TYPE_QCA6290 defined

Change-Id: I4edd5a5b600007ebe7416195648815d80025e768
CRs-Fixed: 1089874
This commit is contained in:
Houston Hoffman
2016-09-19 13:12:30 -07:00
committed by Gerrit - the friendly Code Review server
parent a57184e5ef
commit 31b25ecbea
11 changed files with 318 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
hif/inc/hif.h
View File

@@ -63,6 +63,7 @@ typedef void *hif_handle_t;
#define HIF_TYPE_IPQ4019 13
#define HIF_TYPE_QCA9888 14
#define HIF_TYPE_QCA8074 15
#define HIF_TYPE_QCA6290 16
/* TARGET definition needs to be abstracted in fw common
* header files, below is the placeholder till WIN codebase
@@ -99,6 +100,9 @@ typedef void *hif_handle_t;
#ifndef TARGET_TYPE_QCA8074
#define TARGET_TYPE_QCA8074 20
#endif
#ifndef TARGET_TYPE_QCA6290
#define TARGET_TYPE_QCA6290 21
#endif
/* enum hif_ic_irq - enum defining integrated chip irq numbers
* defining irq nubers that can be used by external modules like datapath

1
hif/inc/hostdef.h
View File

@@ -33,6 +33,7 @@ extern struct hostdef_s *AR6320_HOSTdef;
extern struct hostdef_s *AR900B_HOSTdef;
extern struct hostdef_s *QCA9984_HOSTdef;
extern struct hostdef_s *QCA9888_HOSTdef;
extern struct hostdef_s *QCA6290_HOSTdef;
#ifdef ATH_AHB
extern struct hostdef_s *IPQ4019_HOSTdef;
#endif

2
hif/inc/targetdef.h
View File

@@ -33,6 +33,7 @@ extern struct targetdef_s *AR6320_TARGETdef;
extern struct targetdef_s *AR900B_TARGETdef;
extern struct targetdef_s *QCA9984_TARGETdef;
extern struct targetdef_s *QCA9888_TARGETdef;
extern struct targetdef_s *QCA6290_TARGETdef;
#ifdef ATH_AHB
extern struct targetdef_s *IPQ4019_TARGETdef;
#endif
@@ -47,6 +48,7 @@ extern struct ce_reg_def *AR6320_CE_TARGETdef;
extern struct ce_reg_def *AR900B_CE_TARGETdef;
extern struct ce_reg_def *QCA9984_CE_TARGETdef;
extern struct ce_reg_def *QCA9888_CE_TARGETdef;
extern struct ce_reg_def *QCA6290_CE_TARGETdef;
#ifdef ATH_AHB
extern struct ce_reg_def *IPQ4019_CE_TARGETdef;
#endif

63
hif/src/ce/ce_assignment.h
View File

@@ -474,7 +474,6 @@ static struct CE_pipe_config target_ce_config_wlan_ar900b[] = {
#endif
};
#ifdef QCA_WIFI_QCA8074
static struct CE_attr host_ce_config_wlan_qca8074[] = {
/* host->target HTC control and raw streams */
{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 2048, 0, NULL,},
@@ -535,6 +534,66 @@ static struct CE_pipe_config target_ce_config_wlan_qca8074[] = {
/* Target -> host PKTLOG */
{ /* CE11 */ 11, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
};
#endif
static struct CE_attr host_ce_config_wlan_qca6290[] = {
/* host->target HTC control and raw streams */
{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 2048, 0, NULL,},
/* target->host HTT + HTC control */
{ /* CE1 */ CE_ATTR_FLAGS, 0, 0, 2048, 512, NULL,},
/* target->host WMI */
{ /* CE2 */ CE_ATTR_FLAGS, 0, 0, 2048, 32, NULL,},
/* host->target WMI */
{ /* CE3 */ CE_ATTR_FLAGS, 0, 32, 2048, 0, NULL,},
/* host->target HTT */
{ /* CE4 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
CE_HTT_H2T_MSG_SRC_NENTRIES, 256, 0, NULL,},
/* ipa_uc->target HTC control */
{ /* CE5 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
1024, 512, 0, NULL,},
/* Target autonomous HIF_memcpy */
{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
/* ce_diag, the Diagnostic Window */
{ /* CE7 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
2, DIAG_TRANSFER_LIMIT, 2, NULL,},
/* Target to uMC */
{ /* CE8 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
/* target->host HTT */
{ /* CE9 */ CE_ATTR_FLAGS, 0, 0, 2048, 512, NULL,},
/* target->host HTT */
{ /* CE10 */ CE_ATTR_FLAGS, 0, 0, 2048, 512, NULL,},
/* target -> host PKTLOG */
{ /* CE11 */ CE_ATTR_FLAGS, 0, 0, 2048, 512, NULL,},
};
static struct CE_pipe_config target_ce_config_wlan_qca6290[] = {
/* host->target HTC control and raw streams */
{ /* CE0 */ 0, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
/* target->host HTT */
{ /* CE1 */ 1, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
/* target->host WMI + HTC control */
{ /* CE2 */ 2, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
/* host->target WMI */
{ /* CE3 */ 3, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
/* host->target HTT */
{ /* CE4 */ 4, PIPEDIR_OUT, 256, 256,
(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
/* NB: 50% of src nentries, since tx has 2 frags */
/* ipa_uc->target */
{ /* CE5 */ 5, PIPEDIR_OUT, 1024, 64,
(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
/* Reserved for target autonomous HIF_memcpy */
{ /* CE6 */ 6, PIPEDIR_INOUT, 32, 16384, CE_ATTR_FLAGS, 0,},
/* CE7 used only by Host */
{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0,
(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
/* CE8 used only by IPA */
{ /* CE8 */ 8, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
/* CE9 target->host HTT */
{ /* CE9 */ 9, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
/* CE10 target->host HTT */
{ /* CE10 */ 10, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
/* Target -> host PKTLOG */
{ /* CE11 */ 11, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
};
;
#endif /* __HIF_PCI_INTERNAL_H__ */

3
hif/src/ce/ce_internal.h
View File

@@ -291,7 +291,6 @@ struct CE_dest_desc {
};
#endif /* QCA_WIFI_3_0 */
#ifdef QCA_WIFI_QCA8074
struct ce_srng_src_desc {
uint32_t buffer_addr_lo;
#if _BYTE_ORDER == _BIG_ENDIAN
@@ -369,7 +368,7 @@ struct ce_srng_dest_status_desc {
loop_count:4;
#endif
};
#endif
#define CE_SENDLIST_ITEMS_MAX 12
/**

21
hif/src/ce/ce_main.c
View File

@@ -604,10 +604,9 @@ bool ce_srng_based(struct hif_softc *scn)
struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl);
switch (tgt_info->target_type) {
#ifdef QCA_WIFI_QCA8074
case TARGET_TYPE_QCA8074:
case TARGET_TYPE_QCA6290:
return true;
#endif
default:
return false;
}
@@ -616,10 +615,8 @@ bool ce_srng_based(struct hif_softc *scn)
struct ce_ops *ce_services_attach(struct hif_softc *scn)
{
#ifdef QCA_WIFI_QCA8074
if (ce_srng_based(scn))
return ce_services_srng();
#endif
return ce_services_legacy();
}
@@ -881,7 +878,6 @@ struct CE_handle *ce_init(struct hif_softc *scn,
ce_ring_test_initial_indexes(CE_id, dest_ring,
"dest_ring");
#ifdef QCA_WIFI_QCA8074
/* For srng based target, init status ring here */
if (ce_srng_based(CE_state->scn)) {
CE_state->status_ring =
@@ -917,7 +913,7 @@ struct CE_handle *ce_init(struct hif_softc *scn,
goto error_target_access;
}
#endif
/* epping */
/* poll timer */
if ((CE_state->attr_flags & CE_ATTR_ENABLE_POLL)) {
@@ -1179,8 +1175,7 @@ void ce_fini(struct CE_handle *copyeng)
qdf_timer_free(&CE_state->poll_timer);
}
}
#ifdef QCA_WIFI_QCA8074
if (CE_state->status_ring) {
if ((ce_srng_based(CE_state->scn)) && (CE_state->status_ring)) {
/* Cleanup the datapath Tx ring */
ce_h2t_tx_ce_cleanup(copyeng);
@@ -1200,7 +1195,6 @@ void ce_fini(struct CE_handle *copyeng)
base_addr_CE_space, 0);
qdf_mem_free(CE_state->status_ring);
}
#endif
qdf_mem_free(CE_state);
}
@@ -2088,14 +2082,19 @@ void hif_ce_prepare_config(struct hif_softc *scn)
target_service_to_ce_map_sz =
sizeof(target_service_to_ce_map_ar900b);
break;
#ifdef QCA_WIFI_QCA8074
case TARGET_TYPE_QCA8074:
hif_state->host_ce_config = host_ce_config_wlan_qca8074;
hif_state->target_ce_config = target_ce_config_wlan_qca8074;
hif_state->target_ce_config_sz =
sizeof(target_ce_config_wlan_qca8074);
break;
#endif
case TARGET_TYPE_QCA6290:
hif_state->host_ce_config = host_ce_config_wlan_qca6290;
hif_state->target_ce_config = target_ce_config_wlan_qca6290;
hif_state->target_ce_config_sz =
sizeof(target_ce_config_wlan_qca6290);
break;
}
}

9
hif/src/hif_main.c
View File

@@ -440,13 +440,11 @@ void hif_close(struct hif_opaque_softc *hif_ctx)
static QDF_STATUS hif_hal_attach(struct hif_softc *scn)
{
#ifdef QCA_WIFI_QCA8074
if (ce_srng_based(scn)) {
scn->hal_soc = hal_attach(scn, scn->qdf_dev);
if (scn->hal_soc == NULL)
return QDF_STATUS_E_FAILURE;
}
#endif
return QDF_STATUS_SUCCESS;
}
@@ -657,7 +655,6 @@ int hif_get_device_type(uint32_t device_id,
int ret = 0;
switch (device_id) {
case ADRASTEA_DEVICE_ID:
case ADRASTEA_DEVICE_ID_P2_E12:
*hif_type = HIF_TYPE_ADRASTEA;
@@ -728,6 +725,12 @@ int hif_get_device_type(uint32_t device_id,
HIF_INFO(" *********** QCA8074 *************\n");
break;
case QCA6290_EMULATION_DEVICE_ID:
*hif_type = HIF_TYPE_QCA6290;
*target_type = TARGET_TYPE_QCA6290;
HIF_INFO(" *********** QCA6290EMU *************\n");
break;
default:
HIF_ERROR("%s: Unsupported device ID!", __func__);
ret = -ENODEV;

2
hif/src/hif_main.h
View File

@@ -86,7 +86,7 @@
#define AR6320_FW_2_0 (0x20)
#define AR6320_FW_3_0 (0x30)
#define AR6320_FW_3_2 (0x32)
#define ADRASTEA_DEVICE_ID (0xabcd)
#define QCA6290_EMULATION_DEVICE_ID (0xabcd)
#define ADRASTEA_DEVICE_ID_P2_E12 (0x7021)
#define AR9887_DEVICE_ID (0x0050)
#define AR900B_DEVICE_ID (0x0040)

1
hif/src/pcie/if_pci.c
View File

@@ -2040,6 +2040,7 @@ int hif_pci_bus_configure(struct hif_softc *hif_sc)
}
}
/* todo: consider replacing this with an srng field */
if (hif_sc->target_info.target_type == TARGET_TYPE_QCA8074) {
hif_sc->per_ce_irq = true;
}

217
hif/src/qca6290def.c Normal file
View File

@@ -0,0 +1,217 @@
/*
* Copyright (c) 2016 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#if defined(QCA6290_HEADERS_DEF)
#undef UMAC
#define WLAN_HEADERS 1
#include "lithium_top_reg.h"
#define MISSING 0
#define SOC_RESET_CONTROL_OFFSET MISSING
#define GPIO_PIN0_OFFSET MISSING
#define GPIO_PIN1_OFFSET MISSING
#define GPIO_PIN0_CONFIG_MASK MISSING
#define GPIO_PIN1_CONFIG_MASK MISSING
#define LOCAL_SCRATCH_OFFSET 0x18
#define GPIO_PIN10_OFFSET MISSING
#define GPIO_PIN11_OFFSET MISSING
#define GPIO_PIN12_OFFSET MISSING
#define GPIO_PIN13_OFFSET MISSING
#define MBOX_BASE_ADDRESS MISSING
#define INT_STATUS_ENABLE_ERROR_LSB MISSING
#define INT_STATUS_ENABLE_ERROR_MASK MISSING
#define INT_STATUS_ENABLE_CPU_LSB MISSING
#define INT_STATUS_ENABLE_CPU_MASK MISSING
#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
#define INT_STATUS_ENABLE_ADDRESS MISSING
#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
#define HOST_INT_STATUS_ADDRESS MISSING
#define CPU_INT_STATUS_ADDRESS MISSING
#define ERROR_INT_STATUS_ADDRESS MISSING
#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
#define COUNT_DEC_ADDRESS MISSING
#define HOST_INT_STATUS_CPU_MASK MISSING
#define HOST_INT_STATUS_CPU_LSB MISSING
#define HOST_INT_STATUS_ERROR_MASK MISSING
#define HOST_INT_STATUS_ERROR_LSB MISSING
#define HOST_INT_STATUS_COUNTER_MASK MISSING
#define HOST_INT_STATUS_COUNTER_LSB MISSING
#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
#define WINDOW_DATA_ADDRESS MISSING
#define WINDOW_READ_ADDR_ADDRESS MISSING
#define WINDOW_WRITE_ADDR_ADDRESS MISSING
/* GPIO Register */
#define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING
#define GPIO_PIN0_CONFIG_LSB MISSING
#define GPIO_PIN0_PAD_PULL_LSB MISSING
#define GPIO_PIN0_PAD_PULL_MASK MISSING
/* SI reg */
#define SI_CONFIG_ERR_INT_MASK MISSING
#define SI_CONFIG_ERR_INT_LSB MISSING
#define RTC_SOC_BASE_ADDRESS MISSING
#define RTC_WMAC_BASE_ADDRESS MISSING
#define SOC_CORE_BASE_ADDRESS MISSING
#define WLAN_MAC_BASE_ADDRESS MISSING
#define GPIO_BASE_ADDRESS MISSING
#define ANALOG_INTF_BASE_ADDRESS MISSING
#define CE0_BASE_ADDRESS MISSING
#define CE1_BASE_ADDRESS MISSING
#define CE_COUNT 12
#define CE_WRAPPER_BASE_ADDRESS MISSING
#define SI_BASE_ADDRESS MISSING
#define DRAM_BASE_ADDRESS MISSING
#define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
#define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
#define CLOCK_CONTROL_OFFSET MISSING
#define CLOCK_CONTROL_SI0_CLK_MASK MISSING
#define RESET_CONTROL_SI0_RST_MASK MISSING
#define WLAN_RESET_CONTROL_OFFSET MISSING
#define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
#define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
#define CPU_CLOCK_OFFSET MISSING
#define CPU_CLOCK_STANDARD_LSB MISSING
#define CPU_CLOCK_STANDARD_MASK MISSING
#define LPO_CAL_ENABLE_LSB MISSING
#define LPO_CAL_ENABLE_MASK MISSING
#define WLAN_SYSTEM_SLEEP_OFFSET MISSING
#define SOC_CHIP_ID_ADDRESS MISSING
#define SOC_CHIP_ID_REVISION_MASK MISSING
#define SOC_CHIP_ID_REVISION_LSB MISSING
#define SOC_CHIP_ID_REVISION_MSB MISSING
#define FW_IND_EVENT_PENDING MISSING
#define FW_IND_INITIALIZED MISSING
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
#define SR_WR_INDEX_ADDRESS MISSING
#define DST_WATERMARK_ADDRESS MISSING
#define DST_WR_INDEX_ADDRESS MISSING
#define SRC_WATERMARK_ADDRESS MISSING
#define SRC_WATERMARK_LOW_MASK MISSING
#define SRC_WATERMARK_HIGH_MASK MISSING
#define DST_WATERMARK_LOW_MASK MISSING
#define DST_WATERMARK_HIGH_MASK MISSING
#define CURRENT_SRRI_ADDRESS MISSING
#define CURRENT_DRRI_ADDRESS MISSING
#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
#define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
#define HOST_IS_ADDRESS MISSING
#define MISC_IS_ADDRESS MISSING
#define HOST_IS_COPY_COMPLETE_MASK MISSING
#define CE_WRAPPER_BASE_ADDRESS MISSING
#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
#define HOST_IE_ADDRESS UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0
#define HOST_IE_ADDRESS_2 UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1
#define HOST_IE_COPY_COMPLETE_MASK MISSING
#define SR_BA_ADDRESS MISSING
#define SR_BA_ADDRESS_HIGH MISSING
#define SR_SIZE_ADDRESS MISSING
#define CE_CTRL1_ADDRESS MISSING
#define CE_CTRL1_DMAX_LENGTH_MASK MISSING
#define DR_BA_ADDRESS MISSING
#define DR_BA_ADDRESS_HIGH MISSING
#define DR_SIZE_ADDRESS MISSING
#define CE_CMD_REGISTER MISSING
#define CE_MSI_ADDRESS MISSING
#define CE_MSI_ADDRESS_HIGH MISSING
#define CE_MSI_DATA MISSING
#define CE_MSI_ENABLE_BIT MISSING
#define MISC_IE_ADDRESS MISSING
#define MISC_IS_AXI_ERR_MASK MISSING
#define MISC_IS_DST_ADDR_ERR_MASK MISSING
#define MISC_IS_SRC_LEN_ERR_MASK MISSING
#define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
#define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
#define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
#define SRC_WATERMARK_LOW_LSB MISSING
#define SRC_WATERMARK_HIGH_LSB MISSING
#define DST_WATERMARK_LOW_LSB MISSING
#define DST_WATERMARK_HIGH_LSB MISSING
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
#define CE_CTRL1_DMAX_LENGTH_LSB MISSING
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
#define CE_CTRL1_IDX_UPD_EN_MASK MISSING
#define CE_WRAPPER_DEBUG_OFFSET MISSING
#define CE_WRAPPER_DEBUG_SEL_MSB MISSING
#define CE_WRAPPER_DEBUG_SEL_LSB MISSING
#define CE_WRAPPER_DEBUG_SEL_MASK MISSING
#define CE_DEBUG_OFFSET MISSING
#define CE_DEBUG_SEL_MSB MISSING
#define CE_DEBUG_SEL_LSB MISSING
#define CE_DEBUG_SEL_MASK MISSING
#define CE0_BASE_ADDRESS MISSING
#define CE1_BASE_ADDRESS MISSING
#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
#define QCA6290_BOARD_DATA_SZ MISSING
#define QCA6290_BOARD_EXT_DATA_SZ MISSING
#define MY_TARGET_DEF QCA6290_TARGETdef
#define MY_HOST_DEF QCA6290_HOSTdef
#define MY_CEREG_DEF QCA6290_CE_TARGETdef
#define MY_TARGET_BOARD_DATA_SZ QCA6290_BOARD_DATA_SZ
#define MY_TARGET_BOARD_EXT_DATA_SZ QCA6290_BOARD_EXT_DATA_SZ
#include "targetdef.h"
#include "hostdef.h"
#else
#include "common_drv.h"
#include "targetdef.h"
#include "hostdef.h"
struct targetdef_s *QCA6290_TARGETdef;
struct hostdef_s *QCA6290_HOSTdef;
#endif /*QCA6290_HEADERS_DEF */

14
hif/src/regtable.c
View File

@@ -111,6 +111,14 @@ void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
break;
#endif
#if defined(QCA6290_HEADERS_DEF)
/* use the same defs for HAWKEYE & NAPIER */
case TARGET_TYPE_QCA6290:
scn->targetdef = QCA6290_TARGETdef;
scn->target_ce_def = QCA6290_CE_TARGETdef;
break;
#endif
default:
break;
}
@@ -180,6 +188,12 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
break;
#endif
#if defined(QCA6290_HEADERS_DEF)
case HIF_TYPE_QCA6290:
scn->hostdef = QCA6290_HOSTdef;
break;
#endif
default:
break;
}