msm: camera: utils: Restructure register address validation
On current scheme, we put validation inside IO function, it's hard to block subsequent accessing when facing invalid address and may increase the number of cycles to do the register accessing as well. This change limits the validation to only for the reg dump, we can take following up operations when accessing wrong address for read rather than printing uncertain logs. CRs-Fixed: 3589725 Change-Id: I7d38a3ddb6c3f8e2915070f3c24629754abf76d7 Signed-off-by: Stark Lin <quic_starlin@quicinc.com> (cherry picked from commit 159f8889a51178a92186e66e24e39bfdb01e87ee)
This commit is contained in:
Stark Lin
@@ -3578,13 +3578,30 @@ int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
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return 0;
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}
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static inline int cam_soc_util_reg_addr_validation(
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uint32_t reg_map_size, uint32_t offset, char *reg_unit)
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{
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if (!IS_ALIGNED(offset, 4)) {
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CAM_ERR(CAM_UTIL, "Offset: 0x%X of %s is not memory aligned",
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offset, reg_unit);
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return -EINVAL;
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} else if (offset > reg_map_size) {
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CAM_ERR(CAM_UTIL,
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"Reg offset: 0x%X of %s out of range, reg_map size: 0x%X",
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offset, reg_unit, reg_map_size);
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return -EINVAL;
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}
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return 0;
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}
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static int cam_soc_util_dump_cont_reg_range(
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struct cam_hw_soc_info *soc_info,
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struct cam_reg_range_read_desc *reg_read, uint32_t base_idx,
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struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
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{
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int i = 0, rc = 0, val = 0;
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uint32_t write_idx = 0;
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int i = 0, rc = 0;
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uint32_t write_idx = 0, reg_map_size;
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if (!soc_info || !dump_out_buf || !reg_read || !cmd_buf_end) {
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CAM_ERR(CAM_UTIL,
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@@ -3619,15 +3636,19 @@ static int cam_soc_util_dump_cont_reg_range(
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}
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write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
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reg_map_size = (uint32_t)soc_info->reg_map[base_idx].size;
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for (i = 0; i < reg_read->num_values; i++) {
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val = cam_soc_util_r(soc_info, base_idx,
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(reg_read->offset + (i * sizeof(uint32_t))));
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if (!val)
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CAM_WARN(CAM_UTIL, "Possibly fails to read");
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rc = cam_soc_util_reg_addr_validation(reg_map_size,
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reg_read->offset + (i * sizeof(uint32_t)),
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"cont_reg_range");
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if (rc)
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continue;
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dump_out_buf->dump_data[write_idx++] = reg_read->offset +
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(i * sizeof(uint32_t));
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dump_out_buf->dump_data[write_idx++] = val;
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dump_out_buf->dump_data[write_idx++] =
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cam_soc_util_r(soc_info, base_idx,
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(reg_read->offset + (i * sizeof(uint32_t))));
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dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
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}
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@@ -3640,8 +3661,8 @@ static int cam_soc_util_dump_dmi_reg_range(
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struct cam_dmi_read_desc *dmi_read, uint32_t base_idx,
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struct cam_reg_dump_out_buffer *dump_out_buf, uintptr_t cmd_buf_end)
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{
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int i = 0, rc = 0, val = 0;
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uint32_t write_idx = 0;
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int i = 0, rc = 0;
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uint32_t write_idx = 0, reg_map_size;
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if (!soc_info || !dump_out_buf || !dmi_read || !cmd_buf_end) {
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CAM_ERR(CAM_UTIL,
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@@ -3694,15 +3715,17 @@ static int cam_soc_util_dump_dmi_reg_range(
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}
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write_idx = dump_out_buf->bytes_written / sizeof(uint32_t);
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reg_map_size = (uint32_t)soc_info->reg_map[base_idx].size;
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for (i = 0; i < dmi_read->num_pre_writes; i++) {
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rc = cam_soc_util_w_mb(soc_info, base_idx,
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rc = cam_soc_util_reg_addr_validation(reg_map_size,
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dmi_read->pre_read_config[i].offset,
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"pre_read_config");
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if (rc)
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continue;
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cam_soc_util_w_mb(soc_info, base_idx,
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dmi_read->pre_read_config[i].offset,
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dmi_read->pre_read_config[i].value);
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if (rc) {
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CAM_ERR(CAM_UTIL, "Fails to write for pre_read_config");
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goto end;
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}
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dump_out_buf->dump_data[write_idx++] =
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dmi_read->pre_read_config[i].offset;
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dump_out_buf->dump_data[write_idx++] =
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@@ -3710,26 +3733,30 @@ static int cam_soc_util_dump_dmi_reg_range(
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dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
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}
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for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
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val = cam_soc_util_r_mb(soc_info, base_idx,
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dmi_read->dmi_data_read.offset);
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if (!val)
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CAM_WARN(CAM_UTIL, "Possibly fails to read for dmi_data_read");
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dump_out_buf->dump_data[write_idx++] =
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dmi_read->dmi_data_read.offset;
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dump_out_buf->dump_data[write_idx++] = val;
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dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
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rc = cam_soc_util_reg_addr_validation(reg_map_size,
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dmi_read->dmi_data_read.offset,
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"dmi_data_read");
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if (!rc) {
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for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
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dump_out_buf->dump_data[write_idx++] =
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dmi_read->dmi_data_read.offset;
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dump_out_buf->dump_data[write_idx++] =
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cam_soc_util_r_mb(soc_info, base_idx,
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dmi_read->dmi_data_read.offset);
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dump_out_buf->bytes_written += (2 * sizeof(uint32_t));
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}
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}
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for (i = 0; i < dmi_read->num_post_writes; i++) {
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rc = cam_soc_util_w_mb(soc_info, base_idx,
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rc = cam_soc_util_reg_addr_validation(reg_map_size,
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dmi_read->post_read_config[i].offset,
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"post_read_config");
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if (rc)
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continue;
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cam_soc_util_w_mb(soc_info, base_idx,
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dmi_read->post_read_config[i].offset,
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dmi_read->post_read_config[i].value);
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if (rc) {
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CAM_ERR(CAM_UTIL, "Fails to write for post_read_config");
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goto end;
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}
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}
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end:
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@@ -3743,11 +3770,10 @@ static int cam_soc_util_dump_dmi_reg_range_user_buf(
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{
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int i;
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int rc;
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int val = 0;
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size_t buf_len = 0;
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uint8_t *dst;
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size_t remain_len;
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uint32_t min_len;
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uint32_t min_len, reg_map_size;
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uint32_t *waddr, *start;
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uintptr_t cpu_addr;
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struct cam_hw_soc_dump_header *hdr;
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@@ -3804,37 +3830,43 @@ static int cam_soc_util_dump_dmi_reg_range_user_buf(
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hdr->word_size = sizeof(uint32_t);
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*waddr = soc_info->index;
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waddr++;
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reg_map_size = (uint32_t)soc_info->reg_map[base_idx].size;
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for (i = 0; i < dmi_read->num_pre_writes; i++) {
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rc = cam_soc_util_w_mb(soc_info, base_idx,
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rc = cam_soc_util_reg_addr_validation(reg_map_size,
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dmi_read->pre_read_config[i].offset,
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"pre_read_config");
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if (rc)
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continue;
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cam_soc_util_w_mb(soc_info, base_idx,
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dmi_read->pre_read_config[i].offset,
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dmi_read->pre_read_config[i].value);
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if (rc) {
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CAM_ERR(CAM_UTIL, "Fails to write for pre_read_config");
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goto end;
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}
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*waddr++ = dmi_read->pre_read_config[i].offset;
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*waddr++ = dmi_read->pre_read_config[i].value;
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}
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for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
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val = cam_soc_util_r_mb(soc_info, base_idx,
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dmi_read->dmi_data_read.offset);
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if (!val)
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CAM_WARN(CAM_UTIL, "Possibly fails to read for dmi_data_read");
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*waddr++ = dmi_read->dmi_data_read.offset;
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*waddr++ = val;
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rc = cam_soc_util_reg_addr_validation(reg_map_size,
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dmi_read->dmi_data_read.offset,
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"dmi_data_read");
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if (!rc) {
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for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) {
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*waddr++ = dmi_read->dmi_data_read.offset;
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*waddr++ = cam_soc_util_r_mb(soc_info, base_idx,
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dmi_read->dmi_data_read.offset);
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}
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}
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for (i = 0; i < dmi_read->num_post_writes; i++) {
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rc = cam_soc_util_w_mb(soc_info, base_idx,
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rc = cam_soc_util_reg_addr_validation(reg_map_size,
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dmi_read->post_read_config[i].offset,
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"post_read_config");
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if (rc)
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continue;
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cam_soc_util_w_mb(soc_info, base_idx,
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dmi_read->post_read_config[i].offset,
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dmi_read->post_read_config[i].value);
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if (rc) {
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CAM_ERR(CAM_UTIL, "Fails to write for post_read_config");
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goto end;
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}
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}
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hdr->size = (waddr - start) * hdr->word_size;
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dump_args->offset += hdr->size +
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@@ -3852,11 +3884,11 @@ static int cam_soc_util_dump_cont_reg_range_user_buf(
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struct cam_hw_soc_dump_args *dump_args)
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{
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int i;
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int rc = 0, val = 0;
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int rc = 0;
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size_t buf_len;
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uint8_t *dst;
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size_t remain_len;
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uint32_t min_len;
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uint32_t min_len, reg_map_size;
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uint32_t *waddr, *start;
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uintptr_t cpu_addr;
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struct cam_hw_soc_dump_header *hdr;
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@@ -3902,14 +3934,18 @@ static int cam_soc_util_dump_cont_reg_range_user_buf(
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hdr->word_size = sizeof(uint32_t);
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*waddr = soc_info->index;
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waddr++;
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reg_map_size = (uint32_t)soc_info->reg_map[base_idx].size;
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for (i = 0; i < reg_read->num_values; i++) {
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val = cam_soc_util_r(soc_info, base_idx,
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(reg_read->offset + (i * sizeof(uint32_t))));
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if (!val)
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CAM_WARN(CAM_UTIL, "Possibly fails to read");
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rc = cam_soc_util_reg_addr_validation(reg_map_size,
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reg_read->offset + (i * sizeof(uint32_t)),
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"cont_reg_range_user_buf");
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if (rc)
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continue;
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waddr[0] = reg_read->offset + (i * sizeof(uint32_t));
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waddr[1] = val;
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waddr[1] = cam_soc_util_r(soc_info, base_idx,
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(reg_read->offset + (i * sizeof(uint32_t))));
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waddr += 2;
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}
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hdr->size = (waddr - start) * hdr->word_size;
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