qcacmn: Add reg opclass changes for 320MHZ

Add opclass changes to support 320MHZ in 11BE

CRs-Fixed: 3135023
Change-Id: I57827cf0f5f056df0dceee0a6225d4ea7219cce9

umac/regulatory/core/src/reg_opclass.c

@@ -1447,6 +1447,27 @@ static void reg_get_channel_cen(const struct
 	*idx = *idx + num_channels;
 }
 
+/**
+ * reg_is_chan_320mhz() - Return true if the chan width is 320MHZ,
+ * false otherwise.
+ * @chan_spacing: Channel spacing in MHZ.
+ *
+ * Return: true if chan_width is 320, false otherwise.
+ */
+#ifdef WLAN_FEATURE_11BE
+static bool reg_is_chan_320mhz(uint16_t chan_spacing)
+{
+	if (chan_spacing == BW_320_MHZ)
+		return true;
+	return false;
+}
+#else
+static bool reg_is_chan_320mhz(uint16_t chan_spacing)
+{
+	return false;
+}
+#endif
+
 /**
  * reg_get_chan_or_chan_center - Calculate central channel in the channel set.
  *
@@ -1474,6 +1495,11 @@ static uint8_t reg_get_chan_or_chan_center(const struct
 				    idx,
 				    NUM_20_MHZ_CHAN_IN_160_MHZ_CHAN,
 				    &center_chan);
+	} else if (reg_is_chan_320mhz(op_class_tbl->chan_spacing)) {
+		reg_get_channel_cen(op_class_tbl,
+				    idx,
+				    NUM_20_MHZ_CHAN_IN_320_MHZ_CHAN,
+				    &center_chan);
 	} else {
 		center_chan = op_class_tbl->channels[*idx];
 		*idx = *idx + 1;

umac/regulatory/core/src/reg_services_common.h

@@ -39,6 +39,7 @@
 #define NUM_20_MHZ_CHAN_IN_40_MHZ_CHAN     2
 #define NUM_20_MHZ_CHAN_IN_80_MHZ_CHAN     4
 #define NUM_20_MHZ_CHAN_IN_160_MHZ_CHAN    8
+#define NUM_20_MHZ_CHAN_IN_320_MHZ_CHAN    16
 
 #define REG_MAX_5GHZ_CH_NUM channel_map[MAX_5GHZ_CHANNEL].chan_num
 
@@ -127,7 +128,7 @@
 /* EEPROM setting is a country code */
 #define    COUNTRY_ERD_FLAG     0x8000
 #define MIN_6GHZ_OPER_CLASS 131
-#define MAX_6GHZ_OPER_CLASS 136
+#define MAX_6GHZ_OPER_CLASS 137
 
 #ifdef CONFIG_AFC_SUPPORT
 #define DEFAULT_REQ_ID 11235813

umac/regulatory/dispatcher/inc/reg_services_public_struct.h

@@ -762,7 +762,7 @@ struct reg_dmn_op_class_map_t {
  */
 struct regdmn_ap_cap_opclass_t {
 	uint8_t op_class;
-	uint8_t ch_width;
+	uint16_t ch_width;
 	qdf_freq_t start_freq;
 	uint16_t behav_limit;
 	uint8_t max_tx_pwr_dbm;