disp: msm: dsi: add mutex lock before link clock frequency update
Acquire mngr clk_mutex before updating link clock frequencies. Failing this may lead to race around condition while setting the link clock frequency rates. Make sure byteclk and pclk rates of PLL are configured according to clock manager and not the controller. Change-Id: I2cd26e659ce166d5bc55eb6c060672eeee192bea Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
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*/
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@@ -1114,11 +1114,6 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
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dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;
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dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;
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rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,
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dsi_ctrl->cell_index);
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if (rc)
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DSI_CTRL_ERR(dsi_ctrl, "Failed to update link frequencies\n");
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return rc;
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}
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