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@@ -862,7 +862,6 @@ static int __watchdog_iris2(struct msm_vidc_core *vidc_core, u32 intr_status)
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static int __noc_error_info_iris2(struct msm_vidc_core *vidc_core)
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static int __noc_error_info_iris2(struct msm_vidc_core *vidc_core)
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{
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{
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- u32 val = 0;
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struct msm_vidc_core *core = vidc_core;
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struct msm_vidc_core *core = vidc_core;
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if (!core) {
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if (!core) {
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@@ -870,6 +869,14 @@ static int __noc_error_info_iris2(struct msm_vidc_core *vidc_core)
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return -EINVAL;
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return -EINVAL;
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}
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}
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+ /*
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+ * we are not supposed to access vcodec subsystem registers
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+ * unless vcodec core clock WRAPPER_CORE_CLOCK_CONFIG_IRIS2 is enabled.
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+ * core clock might have been disabled by video firmware as part of
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+ * inter frame power collapse (power plane control feature).
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+ */
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+
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+ /*
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val = __read_register(core, VCODEC_NOC_ERL_MAIN_SWID_LOW);
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val = __read_register(core, VCODEC_NOC_ERL_MAIN_SWID_LOW);
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d_vpr_e("VCODEC_NOC_ERL_MAIN_SWID_LOW: %#x\n", val);
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d_vpr_e("VCODEC_NOC_ERL_MAIN_SWID_LOW: %#x\n", val);
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val = __read_register(core, VCODEC_NOC_ERL_MAIN_SWID_HIGH);
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val = __read_register(core, VCODEC_NOC_ERL_MAIN_SWID_HIGH);
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@@ -896,6 +903,7 @@ static int __noc_error_info_iris2(struct msm_vidc_core *vidc_core)
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d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
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d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
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val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH);
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val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH);
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d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH: %#x\n", val);
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d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH: %#x\n", val);
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+ */
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return 0;
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return 0;
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}
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}
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