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@@ -352,6 +352,24 @@ static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc,
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pm_qos_remove_request(&sde_enc->pm_qos_cpu_req);
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}
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+static bool _sde_encoder_is_autorefresh_enabled(
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+ struct sde_encoder_virt *sde_enc)
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+{
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+ struct drm_connector *drm_conn;
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+
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+ if (!sde_enc->cur_master ||
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+ !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
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+ return false;
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+
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+ drm_conn = sde_enc->cur_master->connector;
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+
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+ if (!drm_conn || !drm_conn->state)
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+ return false;
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+
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+ return sde_connector_get_property(drm_conn->state,
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+ CONNECTOR_PROP_AUTOREFRESH) ? true : false;
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+}
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+
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static bool _sde_encoder_is_dsc_enabled(struct drm_encoder *drm_enc)
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{
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struct sde_encoder_virt *sde_enc;
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@@ -3946,8 +3964,8 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
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u32 pending_kickoff_cnt;
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struct msm_drm_private *priv = NULL;
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struct sde_kms *sde_kms = NULL;
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- bool is_vid_mode = false;
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struct sde_crtc_misr_info crtc_misr_info = {false, 0};
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+ bool is_regdma_blocking = false, is_vid_mode = false;
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if (!sde_enc) {
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SDE_ERROR("invalid encoder\n");
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@@ -3957,6 +3975,9 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
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if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
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is_vid_mode = true;
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+ is_regdma_blocking = (is_vid_mode ||
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+ _sde_encoder_is_autorefresh_enabled(sde_enc));
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+
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/* don't perform flush/start operations for slave encoders */
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for (i = 0; i < sde_enc->num_phys_encs; i++) {
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struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
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@@ -3976,7 +3997,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
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if (!phys->ops.needs_single_flush ||
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!phys->ops.needs_single_flush(phys)) {
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if (ctl->ops.reg_dma_flush)
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- ctl->ops.reg_dma_flush(ctl, is_vid_mode);
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+ ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
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_sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
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} else if (ctl->ops.get_pending_flush) {
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ctl->ops.get_pending_flush(ctl, &pending_flush);
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@@ -3987,7 +4008,7 @@ static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
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if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
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ctl = sde_enc->cur_master->hw_ctl;
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if (ctl->ops.reg_dma_flush)
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- ctl->ops.reg_dma_flush(ctl, is_vid_mode);
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+ ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
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_sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
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&pending_flush);
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}
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