samsung-sm8650/android_kernel_samsung_sm8650-modules
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disp: msm: typecast variables as long long for 64 bit operations

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Define 64 bit variables as unsigned long long to ensure
8 bytes in 32 bit builds.

Change-Id: I723ae0c4ba6a0de07c92d14eeef95bde095c8e3d
Signed-off-by: Venkata Prahlad Valluru <vvalluru@codeaurora.org>
This commit is contained in:
Venkata Prahlad Valluru
2021-01-06 00:52:36 +05:30
committed by Gerrit - the friendly Code Review server
parent 6ec2c7e072
commit 2ec9452162
5 changed files with 17 additions and 16 deletions
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12
msm/dsi/dsi_pll_5nm.c
View File

@@ -270,11 +270,11 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_5nm *pll,
switch (rsc->pll_revision) {
case DSI_PLL_5NM:
default:
if (pll_freq <= 1000000000)
if (pll_freq <= 1000000000ULL)
regs->pll_clock_inverters = 0xA0;
else if (pll_freq <= 2500000000)
else if (pll_freq <= 2500000000ULL)
regs->pll_clock_inverters = 0x20;
else if (pll_freq <= 3500000000)
else if (pll_freq <= 3500000000ULL)
regs->pll_clock_inverters = 0x00;
else
regs->pll_clock_inverters = 0x40;
@@ -369,16 +369,16 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_5nm *pll,
switch (rsc->pll_revision) {
case DSI_PLL_5NM:
default:
if (vco_rate < 3100000000)
if (vco_rate < 3100000000ULL)
DSI_PLL_REG_W(pll_base,
PLL_ANALOG_CONTROLS_FIVE_1, 0x01);
else
DSI_PLL_REG_W(pll_base,
PLL_ANALOG_CONTROLS_FIVE_1, 0x03);
if (vco_rate < 1520000000)
if (vco_rate < 1520000000ULL)
DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x08);
else if (vco_rate < 2990000000)
else if (vco_rate < 2990000000ULL)
DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x00);
else
DSI_PLL_REG_W(pll_base, PLL_VCO_CONFIG_1, 0x01);

7
msm/sde/sde_hw_color_proc_v4.c
View File

@@ -410,10 +410,9 @@ void sde_demura_backlight_cfg(struct sde_hw_dspp *ctx, u64 val)
}
demura_base = ctx->cap->sblk->demura.base;
backlight = (val & REG_MASK(11));
backlight |= ((val & REG_MASK_SHIFT(11, 32)) >> 16);
SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->demura.base + 0x8,
backlight);
backlight = (val & REG_MASK_ULL(11));
backlight |= ((val & REG_MASK_SHIFT_ULL(11, 32)) >> 16);
SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->demura.base + 0x8, backlight);
}
void sde_setup_fp16_cscv1(struct sde_hw_pipe *ctx,

3
msm/sde/sde_hw_reg_dma_v1.c
View File

@@ -880,7 +880,8 @@ static int check_support_v1(enum sde_reg_dma_features feature,
if (!is_supported)
return -EINVAL;
if (feature >= REG_DMA_FEATURES_MAX || blk >= BIT(REG_DMA_BLK_MAX)) {
if (feature >= REG_DMA_FEATURES_MAX
|| blk >= BIT_ULL(REG_DMA_BLK_MAX)) {
*is_supported = false;
return ret;
}

7
msm/sde/sde_hw_reg_dma_v1_color_proc.c
View File

@@ -12,6 +12,7 @@
#include "sde_hwio.h"
#include "sde_hw_lm.h"
#include "sde_dbg.h"
#include "sde_hw_util.h"
/* Reserve space of 128 words for LUT dma payload set-up */
#define REG_DMA_HEADERS_BUFFER_SZ (sizeof(u32) * 128)
@@ -82,8 +83,6 @@
#define DEMURA_MEM_SIZE ((sizeof(struct drm_msm_dem_cfg)) + \
REG_DMA_HEADERS_BUFFER_SZ)
#define REG_MASK(n) ((BIT(n)) - 1)
#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
#define APPLY_MASK_AND_SHIFT(x, n, shift) ((x & (REG_MASK(n))) << (shift))
#define REG_DMA_VIG_GAMUT_OP_MASK 0x300
#define REG_DMA_VIG_IGC_OP_MASK 0x1001F
@@ -4919,8 +4918,8 @@ static int __reg_dmav1_setup_demurav1_cfg0_c_params(
}
for (i = 0; i < len; i++) {
temp[i * 2] = p[i] & REG_MASK(32);
temp[i * 2 + 1] = (p[i] & REG_MASK_SHIFT(10, 32)) >> 32;
temp[i * 2] = p[i] & REG_MASK_ULL(32);
temp[i * 2 + 1] = (p[i] & REG_MASK_SHIFT_ULL(10, 32)) >> 32;
DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",
i * 2, temp[i * 2]);
DRM_DEBUG_DRIVER("0x6c: index %d value %x\n",

2
msm/sde/sde_hw_util.h
View File

@@ -13,6 +13,8 @@
#define REG_MASK(n) ((BIT(n)) - 1)
#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
#define REG_MASK_ULL(n) ((BIT_ULL(n)) - 1)
#define REG_MASK_SHIFT_ULL(n, shift) ((REG_MASK_ULL(n)) << (shift))
#define LP_DDR4_TYPE 0x7
struct sde_format_extended;